ASIC Implementation of Switchable Key AES Cryptoprocessor
Divya A.G1, Srividya P2

1Divya A.G, Department of Vlsi Design and Embedded System Electronics and Communication, SJBIT, Bangalore (Karnataka), India.
2Srividya P, Associate Professor, Department of Electronics and Communication, SJBIT, Bangalore (Karnataka), India.
Manuscript received on 10 July 2013 | Revised Manuscript received on 18 July 2013 | Manuscript Published on 30 July 2013 | PP: 19-21 | Volume-3 Issue-2, July 2013 | Retrieval Number: A0940063113/13©BEIESP
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Abstract: This paper presents the ASIC implementation of switchable key Advanced Encryption standard algorithm Encryption and decryption with power gating. The implementation supports 128 bits, 192 bits and 256 bits key. The design is described using verilog HDL , simulated in VCS synopsys. The RTL is Synthesized in Design Compiler (DC) using Nangate 45nm open cell library and Physical Design is performed in ICC of Synopsys. The Design was clocked at 125M with a throughput of 1.14Gbps and the power consumption of 1.07mw.
Keywords: ASIC, AES, 45nm Cmos Technology, Key Expansion.

Scope of the Article: Application Specific ICs (ASICs)