Optimization of frequency settling time of PLL using 3 rd MASH Sigma Delta Modulator
Govind Singh Patel1, Nripendra Narayan Das2, Sanjeet Kumar Sinha3

1Govind Singh Patel, SEEE, Lovely Professional University, Jalandhar, India.
2Nripendra Narayan Das, Department of IT, Manipal University, Jaipur. India.
3Sanjeet Kumar Sinha, SEEE, Lovely Professional University, Jalandhar, India.
Manuscript received on December 15, 2019. | Revised Manuscript received on December 23, 2019. | Manuscript published on January 10, 2020. | PP: 2853-2859 | Volume-9 Issue-3, January 2020. | Retrieval Number: B6222129219/2020©BEIESP | DOI: 10.35940/ijitee.B6222.019320
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Abstract: To reduce settling time of PLL, an attempt to optimize the parameters has been proposed in this paper. The transient responses of various Phase Locked Loop (PLL) frequency synthesizer have been comparied with their active and passive poles effect. These results are presented on a type-II 3rd order PLL frequency synthesizer employing a 3rd order MASH sigma delta modulator. The simulation results show the improved performance of the fractional frequency synthesizer for the communication system. These results have been simulated using Advanced Design System(ADS) tool. 
Keywords: VCO, FPGA, DCO, Loop Filter, ADPLL, Phase Detector.
Scope of the Article: Frequency Selective Surface