Development of an Efficient Router Based on Network on Chip Network
Geethanjali N1, Rekha K.R2

1Geethanjali N, Research scholar currently pursuing my Ph.D in SJBIT, Affiliated to VTU, M. Tech in Dr AIT College, BE in Dr AIT Bengaluru.
2Dr. Rekha K.R, Presently Working as Professor in the Department of ECE, SJBIT, Bengaluru, Obtained BE in Electronics from Bangalore University, ME from BMS Institute of Technology, Bangalore, and Ph.D in MGR University Chennai
Manuscript received on December 14, 2019. | Revised Manuscript received on December 22, 2019. | Manuscript published on January 10, 2020. | PP: 3542-3546 | Volume-9 Issue-3, January 2020. | Retrieval Number: B7131129219/2020©BEIESP | DOI: 10.35940/ijitee.B7131.019320
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Abstract: A reconfigurable VLSI architecture for router is the main solution for communication interface quality of service go flexibility of network, cost of chip .The proposed architecture dynamically configure itself with respect to hardware modules such as packet based switch, router and data packet size by changing the conditions of communication and it’s requirement at run time .In network on chip were using extended XY algorithm to improve performance of communication. The proposed design work avoids the dead lock and data loss in the path with the help of this design we can achieve high Data through put and low latency .in this paper we are receiving the previous method and approaches of dynamic reconfigurable router in network on chip 
Keywords: System on Chip, Field-Programmable Gate Array, On Chip Network, Router, Dynamic Reconfiguration
Scope of the Article: Networked-Driven Multicourse Chips