Design of Low Power Adders in Digital Circuits Suitable for Power Reduction in Multipliers
S. Jagadeesh Babu1, A. Jawahar2

1S.Jagadeesh Babu*, Assistant Professor, Department of ECE, R.M.K. Engineering College, Chennai, India.
2Dr.A.Jawahar, Professor, Department of ECE, SSN College of Engineering, Chennai, India.
Manuscript received on December 13, 2019. | Revised Manuscript received on December 23, 2019. | Manuscript published on January 10, 2020. | PP: 1657-1662 | Volume-9 Issue-3, January 2020. | Retrieval Number: C8548019320/2020©BEIESP | DOI: 10.35940/ijitee.C8548.019320
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Abstract: Wireless devices are being evolved at an exponential rate. This evolution is focussing on the development of digital circuits which are incorporated into the processors. The evolutionary process involves individually or a combination of three main objectives namely i) Reduction in size ii) Reduction in power iii) Increase in speed. There is always a trade-off among the above said objectives. In specific multiplying operation inside a processor is one of the core areas where much power is being consumed. On the other hand adders are an integral part in the multiplier circuit. So this work concentrates on designing and analyzing power consumption of five adders namely conventional full adder, 3-transistor XOR based full adder, Gate Diffusion Input (GDI) based full adder, Static Energy Recovery Full (SERF) Adder and full adder using modified XOR gate and finding a resultant low power adder which when implemented for the addition process in multiplier will lead to a reduction in power consumption of multiplier. This in turn reduce the overall power consumption of the processor. The adders are designed using LTSPICE XVII in 180nm technology. The resultant Full Adder using modified XOR gate achieves 61.79% less power compared to conventional full adder and is suitable for multipliers. 
Keywords: Full Adder, GDI, Power Consumption, SERF, XOR gate.
Scope of the Article: Digital System and Logic Design