Designing Network Interface Component for Peripheral IP Cores in Networks-on-Chip
Kulkarni Rashmi Manik1, S. Arulselvi2, B. Karthik3
1Kulkarni Rashmi Manik, Research Scholar, Department of ECE, Bharath Institute of Higher Education and Research, Chennai (Tamil Nadu), India.
2S.Arulselvi, Associate Professor, Department of ECE, Bharath Institute of Higher Education and Research, Chennai (Tamil Nadu), India.
3B.Karthik, Associate Professor, Department of ECE, Bharath Institute of Higher Education and Research, Chennai (Tamil Nadu), India.
Manuscript received on 05 February 2019 | Revised Manuscript received on 13 February 2019 | Manuscript published on 28 February 2019 | PP: 329-336 | Volume-8 Issue-4, February 2019 | Retrieval Number: D2794028419/19©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: The Network-Interface-Componant (NIC) is required for IP cores for interconnecting IPs to Routers in NoC. In implementation of NoC, Interface Component is very crucial for adapting IPs in NoC. NIC as a software component occupies processor’s considerable execution time. Processor can be relieved from this overload by introducing separate hardware as NIC. A hierarchical topology for NoC is considered in this research article. In hierarchical topology, each router can connect to eight nodes (IP) of same hierarchy and to a router in next hierarchy. Each node is connected to router port with NIC. The fixed address based routing is implemented in the NOC. The network packet switching based transactions among various nodes is assumed. The implementation of NIC design with options for different IPs (considering existing bus based interfaces) is attempted in this work.
Keyword: NoC, NIC, IPs, PE, ASIC and NS/CS.
Scope of the Article: Computer Network