The Design of Low-Power High-Speed Two-Level Three input XOR gate
Chaitanya Kommu1, A Daisy Rani2

1Chaitanya Kommu*, Department of EEC, GITAM University, Visakhapatnam, AP, India.
2Dr. A Daisy Rani, Department of Instrument Technology, Andhra University, Visakhapatnam, AP, India.
Manuscript received on February 10, 2020. | Revised Manuscript received on February 23, 2020. | Manuscript published on March 10, 2020. | PP: 1813-1818 | Volume-9 Issue-5, March 2020. | Retrieval Number: E2884039520 /2020©BEIESP | DOI: 10.35940/ijitee.E2884.039520
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Abstract: The Large Fan-In and high performance gates are essential to make portable electronic devices. In this paper an efficient realization of three input two level XOR(Exclusive-OR) is presented. The design of low power and high speed proposed XOR gate involves the combination of pass and transmission gates. The main objective to achieve this is based on the selection of input signals to propagate and maintain the good logic swing. Two methods were used to design proposed XOR, one (i.e. Pass_ gate) is purely based on pass transistors with 8 MOSFET’s and second method(Modified_ Pass_ gate) uses transmission gates with 12 transistors. The Modified_ Pass_ gate offers 86.14% and 6.66% of power dissipation reduction compared to static and Pass_ gate XOR respectively and 77.18% and 50.94% less propagation delay compared to static and Pass_ gate XOR respectively, at the supply voltage of 0.7v with input signal frequency of 3GHz. The simulation is performed based on 32nm technology node(PTM-models) using Hspice Synopsis simulation tool. 
Keywords: Compound Gate, Low-Power CMOS, Pass Transistors, Restoration Logics, Static Gate, Transmission Gate.
Scope of the Article: Low-power Design