Design and Verification of High Speed Multiplier
V. V. S. Vijaya Krishna1, K. Sai Krishna2

1V. V. S. Vijaya Krishna, Department of ECE, Vignan University, Vadlamudi (A.P), India.
2K. Sai Krishna, Department of ECE, CVSR College of Engineering, Hyderabad (Telangana), India.
Manuscript received on 10 November 2013 | Revised Manuscript received on 18 November 2013 | Manuscript Published on 30 November 2013 | PP: 66-68 | Volume-3 Issue-6, November 2013 | Retrieval Number: F1351113613/13©BEIESP
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Abstract: Multiplier is one of the essential element for all digital systems such as digital signal processors, microprocessors etc. In this paper, a new high speed multiplier using booth recoding technique is presented. This algorithm can be implemented by using the radix-8 booth recoding process. The proposed multiplier reduces the partial product array by almost 3/4th the size of the bits. This reduction increases the speed of the multiplier. The proposed method can be extended to any higher radix encodings, as well as to any size square and rectangular multipliers. The proposed multiplier is compared with the standard multiplier and two’s complement multiplier using radix-4 MBE technique, demonstrated the good delay performance. These results show that the proposed multiplier is faster compared to other multipliers. The performance of the proposed multiplier is examined using verilog simulator in XILINX 12.4 version.
Keywords: Multiplication, Radix-8 Booth Recoding, Partial Product Array.

Scope of the Article: High Speed Networks