VLSI Architecture for 9 Element Optimized Sorting Network Using 25 Comparator for Image De-Noising
E. Sindhu1, K .Vasanth2

1E.Sindhu, PG Scholar, Department of VLSI System Design, Vidya Jyothi Institute of Technology, Hyderabad (Telanagana), India.
2K.Vasanth, Professor, Department of ECE, Vidya Jyothi Institute of Technology, Hyderabad (Telanagana), India.
Manuscript received on 07 April 2019 | Revised Manuscript received on 20 April 2019 | Manuscript published on 30 April 2019 | PP: 1177-1183 | Volume-8 Issue-6, April 2019 | Retrieval Number: F3735048619/19©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: The paper introduces a parallel VLSI architecture for Codish sorting. The Codish sorting used generate and prune method to optimize the sorting network for 9 elements using 25 comparators. The prune method optimize the location of each comparator thus makes it an optimized solution. The performance of the proposed architecture was compared with different sorting techniques targeted for XCV1000-5bg560. It was found that the proposed architecture for Codish sorting consumes 402 slices, 4200 gate count, operates at 66.46 ns delay and consumes 7mw of power. The proposed VLSI architecture surpasses all standard sorting algorithms in terms of area, speed and power.
Keyword: Optimized Sorting Network, 9-cell Sorting, Rank Ordering, Parallel Architecture.
Scope of the Article: Image Security