TSV Optimized Test Wrapper Design for Fine Grain Partitioned 3D System on Chip
Harpreet Vohra1, Ashima Singh2

1Harpreet Vohra, Assistant Professor*, Department of Electronics and Communication Engineering , Thapar Institute of Engineering & Technology, Patiala.
2Ashima Singh, Assistant Professor, Computer Science and Engineering Department, Thapar Institute of Engineering & Technology, Patiala
Manuscript received on April 20, 2020. | Revised Manuscript received on April 30, 2020. | Manuscript published on May 10, 2020. | PP: 279-285 | Volume-9 Issue-7, May 2020. | Retrieval Number: G4957059720/2020©BEIESP | DOI: 10.35940/ijitee.G4957.059720
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: The 3D System-on-chip (SoC) technology supports the vertical interconnectivity required for the purpose of functional, supply and test access purposes through the use of Through Silicon Vias (TSVs). Little number of available TSVs for test purpose necessitates the optimization of test infrastructure. This paper proposes an algorithm to design the test wrapper for the 3D cores such that the number of the TSVs used per TAM chain are minimized. Test time optimization is done by balancing the lengths of the individual Wrapper chain inside the core. The proposed heuristic firstly distributes the different core elements on the given TAM chains and then uses a diagraph for their insertion ordering to get minimum possible TSV utilization. Simulation results are presented for the different cores of the ITC’02 SoC benchmark circuits. Results show that TSVs can be reduced to 20-30 percent with around 60-70 percent reduction in CPU time utilization for heavy SoCs in comparison to the other proposed techniques. 
Keywords: Optimal test scheduling, Test architecture, SoC Test, Embedded core testing, Wrapper cell design.
Scope of the Article: Service Oriented Architectures