An Optimized Area Efficient High Speed CSD Multiplier for Image Processing Applications
C.Priyanka1, E. RanaPratap2, S. Bhaskar3, Y. Naresh4

1C.Priyanka, Department of ECE, Koneru Lakshmaiah Education Foundation, Vaddeswaram ,Guntur (Andhra Pradesh), India.
2E.RanaPratap, Department of ECE, Koneru Lakshmaiah Education Foundation, Vaddeswaram ,Guntur (Andhra Pradesh), India.
3S.Bhaskar, Department of ECE, Koneru Lakshmaiah Education Foundation, Vaddeswaram ,Guntur (Andhra Pradesh), India.
4Y.Naresh, Department of ECE, Koneru Lakshmaiah Education Foundation, Vaddeswaram ,Guntur (Andhra Pradesh), India.
Manuscript received on 01 May 2019 | Revised Manuscript received on 15 May 2019 | Manuscript published on 30 May 2019 | PP: 1384-1388 | Volume-8 Issue-7, May 2019 | Retrieval Number: G5311058719/19©BEIESP
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Abstract: Multiplier is a basic fundamental element in many digital and analog systems, Digital signal processing and image processing applications. Thus designing an efficient digital multiplier plays a vital role as hardware resources and processing time is considerably more compared to resources and processing time required to perform addition and subtraction. In this paper an high speed Vedic multiplier using CSD algorithm for image processing applications like edge detection is done and observed that high speed i.e. less delay and less area is achieved compared to Dadda multiplier using CSD algorithm. Simulation of this high speed multiplier is done in Xilinx ISE 14.2 tool using verilog programming and comparison among various factors like delay and area is done.
Keyword: Area, CSD Algorithm, Delay, Multiplier.
Scope of the Article: Signal and Image Processing.