Full Adder Designs Using Low Power Full Swing Xor and Xnor Structures
Rajesh Pyla1, L V Santosh Kumar Y2, H K Raghu Vamsi3
1Pyla Rajesh, ECE, Raghu Engineering College, Visakhapatnam, India.
2L V Santosh Kumar Y, ECE, Raghu Engineering College, Visakhapatnam, India.
3H K Raghu Vamsi, ECE, Raghu Engineering College, Visakhapatnam, India.
Manuscript received on 02 June 2019 | Revised Manuscript received on 10 June 2019 | Manuscript published on 30 June 2019 | PP: 198-203 | Volume-8 Issue-8, June 2019 | Retrieval Number: G6279058719/19©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: As the scale of integration increases, the usefulness of the circuit is limited by more power and area consumption. The demand for battery-powered devices such as mobile phones, tablets and laptops is growing. In this paper, two proposed full adder structures are implemented using XOR-XNOR gates. The optimizations of these circuits are going to be in terms of power consumption and delay because the output capacitance of adder is low. The proposed full adder structures consume 0.32µW and 0.34µW of power respectively which is small when compared to other conventional full adder structures. These full adders not only achieves low power and high speed but also give full swing with less number of transistors. To investigate the performance of the circuits Tanner Tools and HSPICE are used. This simulation is based on 90nm technology.
Keyword: Capacitance adder, Delay, Low power, Full-Adder.
Scope of the Article: Sequential, Parallel and Distributed Algorithms and Data Structures