FFT using Power Efficient Vedic Multiplier
Nidhi Gaur1, Anu Mehra2, Pradeep Kumar3

1Nidhi Gaur, Department of ECE, Amity University, Uttar Pradesh, India.
2Anu Mehra, Department of ECE, Amity University, Uttar Pradesh, India.
3Pradeep Kumar, Department of ECE, Amity University, Uttar Pradesh, India..

Manuscript received on 02 July 2019 | Revised Manuscript received on 05 July 2019 | Manuscript published on 30 August 2019 | PP: 603-608 | Volume-8 Issue-10, August 2019 | Retrieval Number: I8922078919/2019©BEIESP | DOI: 10.35940/ijitee.I8922.0881019
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: Modern communication systems rely on Digital Signal Processing (DSP) more than ever before. Improving the speed of FFT computation using high speed multipliers will help to enhance the performance of DSP systems. In this paper a DIT FFT architecture using high performance Modified Vedic multipliers is proposed. Vedic Multipliers offer a more efficient way to perform multiplication on large numbers occupying less area and consuming low power and delay The adders used in the Vedic multipliers are Brent Kung based and multiplexer based adders. The right utilization of these adders at different word lengths helps to achieve an architecture with minimal area and power. Comparative analysis of modified 24×24 Vedic Multiplier with existing Vedic Multiplier shows the improvement in performance with respect to power and area. Proposed FFT design is compared with existing designs for dynamic power consumption and an improvement of 46.93% compared to Tsai’s FFT Design and 59.37% compared to Coelho’s FFT Design is achieved. The entire architecture is implemented on Virtex 7 FPGA and simulated using Xilinx Vivado 2017.4. 
Keywords:  Digital Signal Processing (DSP), Decimation in Time, Fast Fourier Transform, Vedic Multipliers.
Scope of the Article: Digital Signal Processing