High Speed and Low Power Consumption by Exploitation using Novel XOR and XNOR Gates
Swathi Sriramoju1, Sushma Suram2

1Swathi Sriramoju, Department of ECE, Institute of Aeronautical Engineering, Hyderabad (Telangana), India.

2Sushma Suram, Department of ECE, Institute of Aeronautical Engineering, Hyderabad (Telangana), India.

Manuscript received on 14 October 2019 | Revised Manuscript received on 28 October 2019 | Manuscript Published on 26 December 2019 | PP: 1182-1186 | Volume-8 Issue-12S October 2019 | Retrieval Number: K132110812S19/2019©BEIESP | DOI: 10.35940/ijitee.K1321.10812S19

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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open-access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: The present paper proposes a high speed and low power consumption by travelling novel XOR and XNOR gates. The present circuit consist optimized power intakeas well as delay due to small amount produced capacitance and power dissipation for low short circuit. Here we utilize 6 new hybrid 1 bit full adder circuit that produces to and fro XOR/XNOR gates. Here the present circuit has its own advantages like rapidity, power consumption and delay in power product, dynamic capability and so on. Here we proposed signals like HSPICE, Cadence simulations for investigating the performance results which are based on 65-nm CMOS process technical models that indicate high speed and power against FA signals. So here we propose a novel new transistor sizing method that optimizes the PDP circuits. The present circuit investigates on various supply terms of variations like threshold voltages, size of transistors, input noise and output capacitance by utilizing numerical computation particle swam optimization algorithm for achieving desired value in optimum PDP with few iterations.

Keywords: Optimized Power Consumption, Input Noise and Output Capacitance, HSPICE and Cadence Simulations, Particle Swam Optimization Algorithm and Transistor Sizing Algorithm using XOR and XNOR Gates.
Scope of the Article: Low-power design