Volume-11 Issue-5, April 2022 – International Journal of Innovative Technology and Exploring Engineering (IJITEE)

E98360411522

IJITEE Journal — Fri, 08 Apr 2022 09:30:51 +0000

The International Journal of Innovative Technology and Exploring Engineering (IJITEE) has ISSN: 2278-3075 (online), an open-access, peer-reviewed, periodical monthly international journal. This journal is published by Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP) in January, February, March, April, May, June, July, August, September, October, November and December.The journal aims to publish high–quality peer–reviewed original articles in the area of Engineering and Technology that covers Computer Science and Engineering, Information Technology, Electrical and Electronics Engineering, Electronics and Telecommunication, Mechanical Engineering, Civil Engineering and all interdisciplinary streams of Engineering and Technology. #Smart Computing and Information Processing #Signal and Speech Processing #Image Processing and Pattern Recognition #WSN#Artificial Intelligence and machine learning #Data mining and warehousing #Data Analytics #Deep learning #Bioinformatics #High Performance computing #Advanced Computer Networking #Cloud Computing #IoT #Parallel Computing on GPU #Human Computer Interactions #Recent Trends in Microelectronics and VLSI Design #Process & Device Technologies #Low-Power Design #Nanometer-Scale Integrated Circuits #Application specific ICs (ASICs) #FPGAs #Nanotechnology #Nano Electronics and Quantum Computing #3. Challenges of Industry and their Solutions, Communications #Advanced Manufacturing Technologies #Artificial Intelligence #Autonomous Robots #Augmented Reality #Big Data Analytics and Business Intelligence #Cyber Physical Systems (CPS) #Digital Clone or Simulation #Industrial Internet of Things (IIoT) #Manufacturing IoT #Plant Cyber Security #Smart Solutions – Wearable Sensors and Smart Glasses #System Integration #Small Batch Manufacturing #Visual Analytics #Virtual Reality #3D Printing # Internet of Things (IoT) #Internet of Things (IoT) & IoE & Edge Computing #Distributed Mobile Applications Utilizing IoT #Security, Privacy and Trust in IoT & IoE #Standards for IoT Applications #Ubiquitous Computing #Block Chain-enabled IoT Device and Data Security and Privacy #Application of WSN in IoT #Cloud Resources Utilization in IoT #Wireless Access Technologies for IoT #Mobile Applications and Services for IoT #Machine/ Deep Learning with IoT & IoE #Smart Sensors and Internet of Things for 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Motion Based Computer Mouse Control
Pulipati Bhargav¹, Uppalapati Dhanush², Sb Mohammad Ansar³
¹Pulipati Bhargav*, Department of Electronics and Communication Engineering, Vellore Institute of Technology, Tirupati (A. P) India.
²Uppalapati Dhanush, Department of Electronics and Communication Engineering, Vellore Institute of Technology, Tirupati (A. P) India.
³Sb Mohammad Ansar, Department of Electronics and Communication Engineering, Vellore Institute of Technology, Tirupati (A. P) India.
Manuscript received on 20 March 2022. | Revised Manuscript received on 05 April 2022. | Manuscript published on 30 April 2022. | PP: 37-39 | Volume-11 Issue-5, April 2022. | Retrieval Number: 100.1/ijitee.E98360411522 | DOI: 10.35940/ijitee.E9836.0411522
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: This work provides us an efficient way of developing a motion controlled interaction with a computer or laptop without touching it. This is achieved by capturing motion using an external source and processing it to perform the action needed. This work can help a lot of people to save time as they don’t need to come over to perform the task and it can also help people who are physically challenged to use the computer as it is all about making hand moments and interacting with the computer. Our work is based on continuous hand picture acknowledgement framework.
Keywords: Remote Control Cursor, Automatred Cursor
Scope of the Article: Control and Automation

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E98500411522

IJITEE Journal — Fri, 08 Apr 2022 09:21:34 +0000

Design of Low Power and High-Speed Cmos D Flipflop using Supply Voltage Level (SVL) Methods
C.Arunabala¹, A. Lohithakshi², D. Jyothsna³, CH. Pranathi⁴, A. Navaneetha⁵
¹Dr. C. Arunabala*, Department of Electronics & Communication Engineering, Jawaharlal Nehru Technological University, Kakinada. Guntur (A.P), India.
²A. Lohithakshi, Department of Electronics & Communication Engineering, Jawaharlal Nehru Technological University, Kakinada. Guntur (A.P), India.
³D. Jyothsna, Department of Electronics & Communication Engineering, Jawaharlal Nehru Technological University, Kakinada. Guntur (A.P), India.
⁴CH. Pranathi, Department of Electronics & Communication Engineering, Jawaharlal Nehru Technological University, Kakinada. Guntur (A.P), India.
⁵A. Navaneetha, Department of Electronics & Communication Engineering, Jawaharlal Nehru Technological University, Kakinada. Guntur (A.P), India.
Manuscript received on 29 March 2022. | Revised Manuscript received on 04 April 2022. | Manuscript published on 30 April 2022. | PP: 32-36 | Volume-11 Issue-5, April 2022. | Retrieval Number: 100.1/ijitee.E98500411522 | DOI: 10.35940/ijitee.E9850.0411522
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: This Project details about the design of D Flip Flop (DFPFP). This D Flip Flop circuit is analyzed by using the supply voltage level methods. These methods are used mainly to suppress the power consumption caused due to leakage currents. In addition, because of this implemented technique, the time taken for battery backup, and the supply voltage given at standby mode gets minimized. The projected circuit uses a smaller number of transistors, such that power consumption and leakage currents are in prior limit. Mainly, the CMOS D Flip Flops are designed to use them in binary counters, shift registers, Analog and Digital circuit designs. And this circuit design is implemented in 45nm CMOS Technology Cadence Virtuoso Tool.
Keywords: Power Consumption, Leakage Current, 45nm Cmos Technology and Cadence Virtuoso Tool.
Scope of the Article: Low-Power Design

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E98490411522

IJITEE Journal — Fri, 08 Apr 2022 09:13:57 +0000

Design of Diversified Low Power and High-Speed Comparators using 45nm Cmos Technology
C.Arunabala¹, P.V. Sai Ranjitha², Bomminayuni Likhitha Gunturu Sravya³, Bonagiri Navyasree⁴, Arumalla Mounika⁵
¹Dr. C. Arunabala*, Department of Electronics & Communication Engineering, Jawaharlal Nehru Technological University, Kakinada. Guntur (A.P), India.
²P.V.Sai Ranjitha, Department of Electronics & Communication Engineering, Jawaharlal Nehru Technological University, Kakinada. Guntur (A.P), India.
³Bomminayuni Likhitha Gunturu Sravya, Department of Electronics & Communication Engineering, Jawaharlal Nehru Technological University, Kakinada. Guntur (A.P), India.
⁴Bonagiri Navyasree, Department of Electronics & Communication Engineering, Jawaharlal Nehru Technological University, Kakinada. Guntur (A.P), India.
⁵Arumalla Mounika, Department of Electronics & Communication Engineering, Jawaharlal Nehru Technological University, Kakinada. Guntur (A.P), India.
Manuscript received on 29 March 2022. | Revised Manuscript received on 04 April 2022. | Manuscript published on 30 April 2022. | PP: 27-31 | Volume-11 Issue-5, April 2022. | Retrieval Number: 100.1/ijitee.E98490411522 | DOI: 10.35940/ijitee.E9849.0411522
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: At Present, portable battery-operated devices are enhancing due to low power consumption and high-speed applications, The designed circuit with feedback are used to design novel circuits. If the comparator having feedback are without clock signal. The comparators are mainly designed to minimize the power consumption and with good accuracy because of clock signal, if the clock signal is there, it is used to drive the circuit with low current. But in the existed design the circuit is with high power and current. These drawbacks are overcome by using the projected designed comparator. The Projected comparator design is with reduced power consumption, propagation delay, currents and with a smaller number of transistors. The comparators are useful in analog to digital converters. And this is simulated by using 45 nm CMOS technology Cadence Virtuoso tool.
Keywords: Existed Dynamic Comparator, Projected Comparator, 45nm CMOS Technology and Cadence Virtuoso Tool.
Scope of the Article: High Speed Networks

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E98480411522

IJITEE Journal — Fri, 08 Apr 2022 09:05:45 +0000

Design of Various Low Power and Highspeed Full Adder Designs using 45nm Cmos Technology
Soniya Nuthalapati¹, Ch. Jyothirmayi², Galla. Saikiran³, Chaitanya Prathikonda⁴, Arigala Joseph Jagarlamudi Manikanta⁵
¹Soniya Nuthalapati*, Department of Electronics & Communication Engineering, Jawaharlal Nehru Technological University, Kakinada. Guntur (A.P), India.
²Ch. Jyothirmayi, Department of Electronics & Communication Engineering, Jawaharlal Nehru Technological University, Kakinada. Guntur (A.P), India.
³Galla. Saikiran, Department of Electronics & Communication Engineering, Jawaharlal Nehru Technological University, Kakinada. Guntur (A.P), India.
⁴Chaitanya Prathikonda, Department of Electronics & Communication Engineering, Jawaharlal Nehru Technological University, Kakinada. Guntur (A.P), India.
⁵Arigala Joseph Jagarlamudi Manikanta, Department of Electronics & Communication Engineering, Jawaharlal Nehru Technological University, Kakinada. Guntur (A.P), India.
Manuscript received on 29 March 2022. | Revised Manuscript received on 04 April 2022. | Manuscript published on 30 April 2022. | PP: 21-26 | Volume-11 Issue-5, April 2022. | Retrieval Number: 100.1/ijitee.E98480411522 | DOI: 10.35940/ijitee.E9848.0411522
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: This project visualizes the different designs of Full Adder (FADDR) circuits. These FADDR circuits are designed mainly to reduce the power and delay factors. If these two factors are minimized then automatically the power delay product (PDP) gets minimized. In addition, to design the FADDR, we used multiplexer. So, that the FADDR transistor count gets reduced. Here in this FADDR implementation, it is designed with different transistors count and the factors like power consumption propagation delay and power delay product (PDP) constraints are tabulated with different transistor count of FADDR designs. Then the power consumption and propagation delay factors get reduced. The designs are simulated by using 45nm CMOS technology in Cadence Virtuoso tool.
Keywords: Index Terms: Power Consumption, Propagation Delay, 45nm Cmos Technology and Cadence Virtuoso Tool.
Scope of the Article: Low-power design

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E98470411522

IJITEE Journal — Fri, 08 Apr 2022 08:57:00 +0000

Impedance Cardiography Signal Improvement Through Sign Related Adaptive Removers for Remote Health Care
Soniya Nuthalapati¹, Kusuma Nutalapati², Naveen Laghuvarapu Prasad Nagipogu³, P. Yaswanth Sai Mandepudi Koteswararao⁴, Maddineni Venkata Jaya Prakash⁵
¹Soniya Nuthalapati*, Department of Electronics & Communication Engineering, Jawaharlal Nehru Technological University, Kakinada. Guntur (A.P), India.
²Kusuma Nutalapati, Department of Electronics & Communication Engineering, Jawaharlal Nehru Technological University, Kakinada. Guntur (A.P), India.
³Naveen Laghuvarapu Prasad Nagipogu, Department of Electronics & Communication Engineering, Jawaharlal Nehru Technological University, Kakinada. Guntur (A.P), India.
⁴P. Yaswanth Sai Mandepudi Koteswararao, Department of Electronics & Communication Engineering, Jawaharlal Nehru Technological University, Kakinada. Guntur (A.P), India.
⁵Maddineni Venkata Jaya Prakash, Department of Electronics & Communication Engineering, Jawaharlal Nehru Technological University, Kakinada. Guntur (A.P), India.
Manuscript received on 29 March 2022. | Revised Manuscript received on 04 April 2022. | Manuscript published on 30 April 2022. | PP: 16-20 | Volume-11 Issue-5, April 2022. | Retrieval Number: 100.1/ijitee.E98470411522 | DOI: 10.35940/ijitee.E9847.0411522
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: The impedance cardiography (ICG) shows the impedance caused in the heart. The ICG gives a clear and accurate results and the applied techniques reduce artifacts and also mathematical calculations. The ICG signal shows various physiological and non-physiological situations, and can calculate the heart volume. The computational complexity is also a main part for remote health care. The adaptive techniques used in this project reduces or removes the noise in the signal, Improve the signal. Mainly to take over the applied signal, convergence rate, and to reduce computations of the proposed theory, we added the sign and normalized adaptive algorithms to take out the realistic wave. In final, the results are taken out from the outcomes by additionally relating it with the adaptive filter to situate it in the proper format.
Keywords: Convergence Rate, Physiological, Non-Physiological and Adaptive Algorithms.
Scope of the Article: Healthcare Informatics

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E98520411522

IJITEE Journal — Sat, 02 Apr 2022 09:35:07 +0000

Utilising Natural Language Processing to Assist ESL Learners in Understanding Parts of Speech
Satwika Nindya Kirana¹, Yash Munnalal Gupta²
¹Satwika Nindya Kirana, Business Management and Languages, Faculty of Management Science, Silpakorn University, Petchaburi, 76120, Thailand.
²Dr. Yash Munnalal Gupta*, Department of Biology, Faculty of Science, Naresuan University, Phitsanulok, 65000, Thailand.
Manuscript received on 29 March 2022. | Revised Manuscript received on 02 April 2022. | Manuscript published on 30 April 2022. | PP: 12-15 | Volume-11 Issue-5, April 2022. | Retrieval Number: 100.1/ijitee.E98520411522 | DOI: 10.35940/ijitee.E9852.0411522
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: The field of Natural Language Processing (NLP) is growing rapidly, as is the number of companies investing in this technology. NLP is changing the way we learn and teach languages. However, it has not been used in ways that benefit ESL (English as a Second Language) educators. It is implied that there is a gap in the application and the use of an NLP tool that focuses on English Part of Speech (POS) analysis to aid the English teaching and learning process. Herein, in this paper, we discuss the prospect of utilising POS analyser to accommodate ESL educators in teaching English POS. The tool development is divided into two sections: 1) the development of a POS analyser; and 2) the implementation of an interface to make the tool become a user-friendly application. We use SpaCy, an NLP opensource library, for the English POS analysis. It offers both statistical and neural network models. It also comes with pre-trained models that can predict the POS. This paper also provides Graphical User Interface (GUI) tool that can be used to create effective and engaging English language teaching materials for learners. GUI tool is created using python programming language. Thus, we first review the NLP-based applications for ESL education, followed by an introduction and overview of our simple POS analysis tool, which is customizable. In the future, we intend to evaluate our tool with the help of ESL educators who are not computer scientists or linguists. The python script used to develop tool is provided at Github: https://github.com/yashmgupta/literate-robot
Keywords: English as a Second Language (ESL), Natural Language Processing (NLP), Part of Speech (POS), Syntax
Scope of the Article: Natural Language Processing

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E98330411522

IJITEE Journal — Sat, 26 Mar 2022 11:25:33 +0000

Big Mart Sales Analysis
Vidya Chitre¹, Shruti Mahishi², Sharvari Mhatre³, Shreya Bhagwat⁴
¹Vidya Chitre, Professor, Department of Information Technology, Vidyalankar Institute of Technology, Mumbai (Maharashtra), India.
²Shruti Mahishi*, Final Year Engineering Student, Department of Information Technology, Vidyalankar Institute of Technology, Mumbai (Maharashtra), India.
³Sharvari Mhatre, Final Year Engineering Student, Department of Information Technology, Vidyalankar Institute of Technology, Mumbai (Maharashtra), India.
⁴Shreya Bhagwat, Final Year Engineering Student, Department of Information Technology, Vidyalankar Institute of Technology, Mumbai (Maharashtra), India.
Manuscript received on March 12, 2022. | Revised Manuscript received on March 21, 2022. | Manuscript published on April 30, 2022. | PP: 8-11 | Volume-11 Issue-5, April 2022. | Retrieval Number: 100.1/ijitee.E98330411522 | DOI: 10.35940/ijitee.C9833.0411522
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: In the modern era of reaching new lengths of advancement, every company and enterprise are working on their customer demands as well as their inventory management. The models used by them help them predict future demands by understanding the pattern from old sales records. Lately, everyone is abandoning the traditional prediction models for sales forecasting as it takes a prolonged amount of time to get the expected results. Therefore now the retailers keep track of their sales record in the form of a data set, which comprises price tag, outlet types, outlet location, item visibility, item outlet sales etc.
Keywords: Analysis, Big Mart, Data Science, Machine Learning, Prediction, Regression, XG Boost
Scope of the Article: Machine Learning

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E98290411522

IJITEE Journal — Fri, 25 Mar 2022 10:09:52 +0000

Optimum Choice of Fabric for Apparel Based on GSM and Yarn Count
Jyothirmai S¹, S. Amsamani²
¹Jyothirmai S, Associate Professor, Department of Textile Design, National Institute of Fashion Technology, Hyderabad (Telangana), India.
²Dr. S. Amsamani, Professor, Department of Textiles and Clothing, Avinashilingam Institute for Home Science and Higher Education for Women, Coimbatore (Tamil Nadu), India.
Manuscript received on March 12, 2022. | Revised Manuscript received on March 21, 2022. | Manuscript published on April 30, 2022. | PP: 6-7 | Volume-11 Issue-5, April 2022. | Retrieval Number: 100.1/ijitee.E98290411522 | DOI: 10.35940/ijitee.E9829.0411522
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: With the variety of fabrics available it is important to understand which GSM and yarn count consumer chooses before buying the final decision to buy apparel. This article is to understand what GSM and yarn count consumers optimally choose and why.
Keywords: Grams per Square Meter (GSM), Yarn count, Thread Count.
Scope of the Article: Textile Engineering

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E98210411522

IJITEE Journal — Fri, 25 Mar 2022 09:47:52 +0000

Comparative Studies on Influence of Tool Geometry on Heat Generation in Friction Stir Welding Process
Pavan Kumar Thimmaraju¹, G. Chandra Mohan Reddy², Krishnaiah Arkanti³
¹Pavan Kumar Thimmaraju*, Department of Mechanical Engineering, Osmania University, Hyderabad (Telangana), India.
²Dr. G.Chandra Mohan Reddy, Department of Mechanical Engineering, Chaitanya Bharathi Institute of Technology, Hyderabad (Telangana), India.
³Dr. Krishnaiah Arkanti, Department of Mechanical Engineering, Osmania University, Hyderabad (Telangana), India.
Manuscript received on 12 March 2022 | Revised Manuscript received on 21 March 2022 | Manuscript published on 30 April 2022. | PP: 1-5 | Volume-11 Issue-5, April 2022. | Retrieval Number: 100.1/ijitee.E98210411522 | DOI: 10.35940/ijitee.C9821.0411522
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: Friction Stir (FS) welding offers a number of advantages over the conventional fusion welding process, and it is used to join aluminum alloys that are difficult to weld by fusion welding processes. It has compatibility to any alloy composition, and produces the welded joints by eliminating the defects with improved mechanical properties. The weld quality is mainly influenced by the heat generated and material flow pattern that takes place during the friction stir welding process which depends on the above mentioned parameters. The mechanical and micro structural properties are highly influenced by the heat generation and material flow patterns. The tool geometry plays a vital role in the heat generation and material flow. The aim of the research is to study the influence of tool geometry on heat generation and temperature during friction stir welding process. A comparative study has been done based on the results obtained from numerical analysis and experimentation. It was found that the dissimilar FS welded joints fabricated using hexagonal tool pin profile generates optimum heat generation and temperature required for formation of quality weld irrespective of other process parameter.
Keywords: Friction Stir Welding, Heat Generation, Tool Geometry, Thermography, Temperature.
Scope of the Article: Welding Technology

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