Volume-3 Issue-1, June 2013 – International Journal of Innovative Technology and Exploring Engineering (IJITEE)

A0925063113

IJITEE Journal — Tue, 03 Jan 2023 08:51:25 +0000

The International Journal of Innovative Technology and Exploring Engineering (IJITEE) has ISSN: 2278-3075 (online), an open-access, peer-reviewed, periodical monthly international journal. This journal is published by Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP) in January, February, March, April, May, June, July, August, September, October, November and December.The journal aims to publish high–quality peer–reviewed original articles in the area of Engineering and Technology that covers Computer Science and Engineering, Information Technology, Electrical and Electronics Engineering, Electronics and Telecommunication, Mechanical Engineering, Civil Engineering and all interdisciplinary streams of Engineering and Technology. #Smart Computing and Information Processing #Signal and Speech Processing #Image Processing and Pattern Recognition #WSN#Artificial Intelligence and machine learning #Data mining and warehousing #Data Analytics #Deep learning #Bioinformatics #High Performance computing #Advanced Computer Networking #Cloud Computing #IoT #Parallel Computing on GPU #Human Computer Interactions #Recent Trends in Microelectronics and VLSI Design #Process & Device Technologies #Low-Power Design #Nanometer-Scale Integrated Circuits #Application specific ICs (ASICs) #FPGAs #Nanotechnology #Nano Electronics and Quantum Computing #3. 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Modified Version of Playfair Cipher using Linear Feedback Shift Register and Transpose Matrix Concept
Vinod Kumar¹, Santosh Kr Upadhyay², Satyam Kishore Mishra³, Devesh Singh⁴
¹Vinod Kumar, Department of Computer Science and Engineering, Mewar University, Chittorgarh (Rajasthan), India.
²Santosh Kumar Upadhyay, Department of Computer Science and Engineering, Mewar University, Chittorgarh (Rajasthan), India.
³Sattyam Kishor Mishra, Department of Computer Science & Engineering, Meerut Institute of Engineering and Technology, Meerut (Uttar Pradesh), India.
⁴Davesh Singh, Department of Computer Science and Engineering, Meerut Institute of Engineering and Technology, Meerut (Uttar Pradesh), India.
Manuscript received on 11 June 2013 | Revised Manuscript received on 17 June 2013 | Manuscript Published on 30 June 2013 | PP: 257-261 | Volume-3 Issue-1, June 2013 | Retrieval Number: A0925063113/13©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: In this paper we are presenting a new technique for secure transmission of message by modified version of playfair cipher combining with random number generator and transpose of matrix concept. To develop such method of encryption technique we have used one of the simplest methods of random number generator called Linear Feedback Shift Register and Transpose Matrix concept has been used. The previous playfair cipher method is based on polyalphabetic cipher which is relatively easy to break because it leaves much of loop hole and a small hundreds of letters of cipher text are sufficient. Here we are generating random number sequences and placing it into 6X6 matrix. Then finding the transpose of it and mapping it to secret key of playfair cipher method. Corresponding number s will be transmitted to the receiver instead of alphabetic numeric key. This method increases security of the transmitted key over unsecured transmission media.
Keywords: Random number, Playfair Cipher, Poly-alphabetic-Numeric Cipher, Linear Feedback Shift Register.
Scope of the Article: Approximation and Randomized Algorithms

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A0960063113

IJITEE Journal — Tue, 03 Jan 2023 08:44:37 +0000

On-Chip High Speed Optical Interconnect with RLCG Electrical Interconnect: Challenges and Dimensions
Nemi Chand Neel¹, Ajay Kumar Banyal², Manu Kumar Sharma³
¹Nemi Chand Neel, Department of Electronics and Communication Engineering, Baldev Ram Mirdha Institute of Technology, Jaipur (Rajasthan), India.
²Ajay Kumar Banyal, Department of Electronics and Communication Engineering, Baldev Ram Mirdha Institute of Technology, Jaipur (Rajasthan), India.
³Manu Kumar Sharma, Department of Electronics and Communication Engineering, Baldev Ram Mirdha Institute of Technology, Jaipur (Rajasthan), India.
Manuscript received on 11 June 2013 | Revised Manuscript received on 17 June 2013 | Manuscript Published on 30 June 2013 | PP: 251-256 | Volume-3 Issue-1, June 2013 | Retrieval Number: A0960063113/13©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: Intrachip optical interconnects(OIs) have the potential to outperform electrical wires and to ultimately solve the communication bottleneck in high-performance integrated circuits. Performance targets and critical directions for Ics progress are yet to be fully explored. In this paper, the International Technology Roadmap for Semiconductors (ITRS) is used as a reference to explore the requirements that silicon-based Ics must satisfy to successfully outperform copper electrical interconnects (IEs). Consiering the state-of-art devices, these requirements are extended to specific IC components.
Keywords: Integrated Optoelectronic Circuits, Optoelectron Ics, Optical Interconnects(Ics), Silicon Photonics.
Scope of the Article: High Speed Networks

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A0953063113

IJITEE Journal — Tue, 03 Jan 2023 07:47:09 +0000

Scalar Multiplication Algorithms of Elliptic Curve Cryptography over GF (2^m )
Praful Kumar Singh¹, Mrityunjay Kumar Choudhary²
¹Mrityunjay Kumar Choudhary, Master M.Tech Degree, Department of Program Information Technology, USICT, GGSIPU, India.
²Praful Kumar Singh, Master M.Tech Degree, Department of Information Technology, USICT, GGSIPU, India.
Manuscript received on 11 June 2013 | Revised Manuscript received on 17 June 2013 | Manuscript Published on 30 June 2013 | PP: 246-250 | Volume-3 Issue-1, June 2013 | Retrieval Number: A0953063113/13©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: Since the inception of elliptic curve cryptography by Koblitz [1] and Miller [2] for implementing public-key protocols as the Diffie-Hellman key agreement, elliptic curve cryptography has become one of the most researched area for providing one stop reliable and secure solution in the field of cryptography. The ECC covers all relevant asymmetric cryptographic primitives like digital signature (ECDSA), key exchange and agreement protocols. Point multiplication serves as the basic building block in all ECC primitives and is the computationally most expensive operation and our analysis revolves around this concept. This paper gives an introduction to Elliptic Curve Cryptography and deals with evaluation of fast scalar multiplication with parallelization of field operation and point addition/multiplication. Elliptic curve cryptography offers best optimized solution with minimum resources like Low memory, High Throughput, low power consumption and minimum key length for the same level of security as compared to its counterpart like RSA, DSA etc. in public key cryptography domain. The work is based on the extensive research work done by Julio Lopez, Ricardo Dahab, Montgomery and other pioneer scientists and academicians in the field of elliptic curve cryptography. Given the importance of Scalar multiplication , we focused ourselves on the Fast Multiplication on Elliptic Curves over finite Binary field GF(2m ) without Pre-computation whose background is set by Julio Lopez et al. in [1], because the finite field operations can be implemented very efficiently in hardware and software.
Keywords: Elliptic Curve Cryptography, Scalar Multiplication, Encryption.
Scope of the Article: Web Algorithms

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A0951063113

IJITEE Journal — Tue, 03 Jan 2023 07:38:39 +0000

Analysis of ZigBee (IEEE 802.15.4 Standard) for Star Topology with AODV Protocol
Priyanka Singh¹, Mukesh Kumar², A. K. Jaiswal³, RohiniSaxena⁴
¹Ms. Priyanka Singh, Department of Electronics Communication & Engineering, SHIATS Allahabad (U.P), India.
²Mukesh Kumar, Assistant Professor, Department of Electronics Communication & Engineering, SHIATS Allahabad (U.P), India.
³A.K.Jaiswal, Professor HOD, Department of Electronics Communication & Engineering, SHIATS Allahabad (U.P), India.
⁴Rohini Saxena, Assistant Professor, Department of Electronics Communication & Engineering, SHIATS Allahabad (U.P), India.
Manuscript received on 11 June 2013 | Revised Manuscript received on 17 June 2013 | Manuscript Published on 30 June 2013 | PP: 243-245 | Volume-3 Issue-1, June 2013 | Retrieval Number: A0951063113/13©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: ZigBee is a new wireless technology based on the 802.15.4 standard which is extensively used in wireless communication. This is designed for applications like wireless monitoring and control of lights, security alarms, motion sensors, thermostats and smoke detectors. ZigBee technology provides a low data rate, low power, and low cost wireless networking on the device-level communication. IEEE 802.15.4 specifies physical and media access control layers. The MAC layer defines different network topologies, namely a star, tree and mesh topology. In this paper, we give a brief overview of ZigBee (IEEE 802.14.5 standard) which is the fundamental of low rate-wireless personal area network (LR-WPAN).Then we analysis the performance of ZigBee (IEEE 802.15.4) for star topology with different traffic scenarios namely CBR, FTP, and Poissonusing the simulation tool NS-2.
Keywords: LR-WPANs, NS-2, ZigBee.
Scope of the Article: Routing and Transport Protocols

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A0950063113

IJITEE Journal — Tue, 03 Jan 2023 07:29:31 +0000

Digital PI Controller using Anti-Wind-Up Mechanism for A Speed Controlled Electric Drive System
Srikanth Mandarapu¹, Sreedhar Lolla², M. V. Suresh Kumar³
¹Srikanth Mandarapu, Department of Electrical & Electronics Engineering, JNTUK, Pydah College of Engineering & Technology, Visakhapatnam (A.P), India.
²Sreedhar Lolla, Department of Electrical & Electronics Engineering, JNTUK, Pydah College of Engineering & Technology, Visakhapatnam (A.P), India.
³M.V. Suresh Kumar, Department of Electrical & Electronics Engineering, JNTUK, Raghu Engineering College, Visakhapatnam (A.P), India.
Manuscript received on 11 June 2013 | Revised Manuscript received on 17 June 2013 | Manuscript Published on 30 June 2013 | PP: 239-242 | Volume-3 Issue-1, June 2013 | Retrieval Number: A0950063113/13©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: This paper discusses the implementation of Digital PI Controller Using Anti Wind-Up Mechanism For A Speed Controlled Electric Drive System. To eliminate the system zeros relocated proportional integral controller is implemented. Which in turn reduces the over shoots. The torque is not limited, inspite of the use of relocated proportional integral controller. The motor windings get damaged, if the torque reaches higher values. In order to limit this torque, we introduce a torque limiter, which limits the torque value to the permissible limits. Due to limited torque, over shoots are produced for large inputs. To eliminate these overshoots, with limited torque, we implement the anti-windup mechanism. The scheme is implemented in MATLAB and from the obtained results its possible use and limitations are studied for torque limits varying from +3000 to +7000 N-m.
Keywords: Anti Wind –Up, Digital Pi Controller, Quantizer, Torque Limiter.
Scope of the Article: Digital System and Logic Design

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A0941063113

IJITEE Journal — Tue, 03 Jan 2023 07:21:34 +0000

Countermeasures for Security Vulnerability in Android
Ipta Thakur¹, Guide-Shaily Jain²
¹Ipta Thakur, Department of CSE, Chitkara University, (Delhi), India.
²Shaily Jain, Department of CSE, Chitkara University, Baddi (Himachal Pradesh), India.
Manuscript received on 11 June 2013 | Revised Manuscript received on 17 June 2013 | Manuscript Published on 30 June 2013 | PP: 235-238 | Volume-3 Issue-1, June 2013 | Retrieval Number: A0941063113/13©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: The high speed penetration of Smartphone’s in the market with Android as the leading operating system makes the need for malware analysis on this platform an urgent and concerning issue. In our project we capitalize earlier approaches for dynamic analysis of location based and other suspicious permissions and classes which can cause vulnerability. Our framework has been demonstrated by analyzing the permissions those are vulnerable. Array list will be created on the basis of the permissions and names of classes, and then checked for vulnerabilities using automated approach and then assured through the manual cross checking for vulnerability.
Keywords: Android Security, Malware Analysis, Dynamic Analysis, Vulnerabilities.
Scope of the Article: Security Service Systems

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A0932063113

IJITEE Journal — Tue, 03 Jan 2023 07:15:17 +0000

A Dynamic Priority Based Arbitration Algorithm
Sandra Mohan¹, Anish Joseph²
¹Mrs. Sandra Mohan, Department of Electronics and Communication Engineering, Sree Buddha College of Engineering, Alappuzha (Kerala), India.
²Mr. Anish Joseph, Technical Staff Engineer, DSipher Design Solutions Pvt Ltd, Bangalore (Karnataka), India.
Manuscript received on 11 June 2013 | Revised Manuscript received on 17 June 2013 | Manuscript Published on 30 June 2013 | PP: 232-234 | Volume-3 Issue-1, June 2013 | Retrieval Number: A0932063113/13©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: Today’s electronic industry consists of chips with multimillion gates. This new level of integration on a single chip is called the System on Chip (SoC) design. In an SoC, on-chip interconnection networks are mostly implemented using buses. The performance of the SoC design heavily depends upon the efficiency of its bus structure. The bus used in the SoC platform requires an arbitration process since multiple components connected to it can act as masters and hence initiate a transaction. As the number of system components in SoC design increases, it becomes that an efficient arbiter is one of the most critical factors for high system performance. This paper deals with an Advanced High-performance Bus (AHB) arbiter with a dynamic arbitration mechanism.
Keywords: AHB, AMBA, Arbiter, SoC.
Scope of the Article: Algorithm Engineering

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A0924063113

IJITEE Journal — Tue, 03 Jan 2023 07:05:29 +0000

Comparative Study of Domain Driven Data Mining for It Infrastructure Suport
V. R. Elangovan¹, E. Ramaraj²
¹V.R Elangovan, Research Scholar, Madurai Kamarajar University Madurai (Tamil Nadu), India.
²E.Ramaraj, Professor, Department of Computer Science and Engineering, Alagappa University, Karaikudi (Tamil Nadu), India.
Manuscript received on 11 June 2013 | Revised Manuscript received on 17 June 2013 | Manuscript Published on 30 June 2013 | PP: 225-231 | Volume-3 Issue-1, June 2013 | Retrieval Number: A0924063113/13©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: Information Technology (IT) is one of the most emerging fields in today’s Internet world. IT can be defined in various ways, but is broadly considered to encompass the use of computers and telecommunications equipment to store, retrieve, transmit and manipulate data. Infrastructure is the base for everything. IT also has an infrastructure, which can be managed and maintained properly. For an organization’s Information Technology, Infrastructure Management (IM) is the management of essential operation components, such as policies, processes, equipment, data, human resources and external contacts. This paper, propose a methodology to manage the IT Infrastructure in a better way. In the proposed methodology uses the tree-structure based architecture to manage the infrastructure with less manual power. To maintain such services, we have to set up an infrastructure and also provide essential steps to maintain and manage those kinds of services. This kind of management is termed as IT Infrastructure Management Services. While the user wants to use this kind of IT Services, the infrastructure paves way for this by providing proper responses for the requests made by the user. These responses are provided by the IT resource persons who are managing and maintaining the services. The proposed methodology deals with this by undertaking the requests from the user and providing proper responses for the requests. The response is provided by analyzing the requests and then redirecting the requests to the resource person who are considering that kind of request. Thus the proposed methodology provides proper services for the user by managing the work flow in the IT Infrastructure. This paper also compared with the other methods in the domain driven data mining area, to ensure that the proposed method is more efficient in terms of SLA service level agreement and methodology when compared to other methods.
Keywords: (IM) (IT).
Scope of the Article: Data Mining

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A0918063113

IJITEE Journal — Tue, 03 Jan 2023 06:59:48 +0000

FPGA Implementation of Booth’s and Baugh-Wooley Multiplier using Verilog
Manish Chaudhary¹, Mandeep Singh Narula²
¹Manish Chaudhary, Department of ECE, ITM University, Gurgaon (Haryana), India.
²Mandeep Singh Narula, Assistant Professor, Department of ECE, ITM University, Gurgaon (Haryana), India.
Manuscript received on 11 June 2013 | Revised Manuscript received on 17 June 2013 | Manuscript Published on 30 June 2013 | PP: 221-224 | Volume-3 Issue-1, June 2013 | Retrieval Number: A0918063113/13©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: Here, in this paper we have designed and implemented a Signed-Unsigned Booth’s Multiplier and a Signed-Unsigned Baugh-Wooley Multiplier for 32-bits multiplication. The designing and verification is done through verilog on Xilinx 12.4. In this paper we tried to explain the step by step process that was adopted for Signed-Unsigned Booth’s Multiplier. Also, two different approaches for implementing the Signed Baugh-Wooley multiplier in Singed-Unsigned Baugh-Wooley multiplier and after, the implementation we could see the differences in certain parameters. The array structure of Signed-Unsigned Booth’s Multiplier and Signed-Unsigned Baugh-Wooley Multiplier is obtained from RTL synthesis are shown. Different parameters like power, CPU usage, CPU time, memory usage etc. have been compared.
Keywords: Array, Booth, Baugh-Wooley, Signed, Unsigned, Verilog.
Scope of the Article: FPGAs

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A0913063113

IJITEE Journal — Tue, 03 Jan 2023 06:53:01 +0000

Gait Recogniton System for Human Identification using BPNN Classifier
Oshin Sharma¹, Sushil Kumar Bansal²
¹Oshin Sharma, Department of Computer Science, Chitkara University, Baddi (Himachal Pradesh), India.
²Sushil Kumar Bansal, Department of Computer Science, Chitkara University, Baddi (Himachal Pradesh), India.
Manuscript received on 11 June 2013 | Revised Manuscript received on 17 June 2013 | Manuscript Published on 30 June 2013 | PP: 217-220 | Volume-3 Issue-1, June 2013 | Retrieval Number: A0913063113/13©BEIESP
Open Access | Editorial and Publishing Policies | Cite | Mendeley | Indexing and Abstracting
© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: Recognition of any individual is a task to identify people. Human recognition methods such as face, fingerprints, and iris generally require user’s cooperation, physical contact or close proximity. These methods are not able to recognize an individual at a distance therefore recognition using gait is relatively new biometric technique without these disadvantages. Human identification using Gait is method to identify an individual by the way he walk or manner of moving on foot. Gait offers ability of distance recognition or at low resolution. In this paper, firstly binary silhouette of a walking person is detected from each frame. Secondly, feature from each frame is extracted using image processing operation. Here center of mass, step size length, and cycle length are talking as key feature. At last BPNN technique is used for training and testing purpose. Here all experiments are done on gait database and input video.
Keywords: Backpropagation Neural Network (BPNN), Gait Recognition, Silhouette Images, Background Subtraction, Features Extraction.
Scope of the Article: System Integration

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