A Novel S-box Generation of AES using Elliptic Curve Cryptography (ECC)
Sapna Kumari. C¹, K. V. Prasad^2
1Sapna Kumari C, Ph.D Research Scholar, Jain University, Bangalore (Karnataka), India.
²K.V. Prasad, Professor & HOD, Department of ECE, Bangalore Institute of Technology, Bangalore (Karnataka), India.
Manuscript received on 05 February 2019 | Revised Manuscript received on 13 February 2019 | Manuscript published on 28 February 2019 | PP: 749-765 | Volume-8 Issue-4, February 2019 | Retrieval Number: D2743028419/19©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: In recent decades, the security of the data is playing a major role in communication systems due to more attackers between the channel media. The security level is depending on secret key, as per literature survey of ECC guide, higher the bits size of the keys, higher the security [19]. Therefore the generation of key with large size is the major challenging task. At present, Advanced Encryption Standard (AES) is a better cryptography system where the encryption and decryption can be performed with fixed key size of 128bits, 192 bits and 256 bits. The security level has been increased in AES due to the S-Box and it consists of 256 different values in the form of 16×16 matrixes, but to generate 256 values the Galois Field (GF) has been used. GF requires a lot of hardware resources with more number of arithmetic operations like multiplication, additions and inversions [20-21]. To overcome this issue, a novel S-Box generation using Elliptic Curve Cryptography (ECC )and BWMC methods are proposed. The ECC uses point addition and point doubling to generate 256 values without multiplication operations. After generation of the matrix, its values are encrypted and decrypted using bitwise matrix code (BWMC). The proposed work has been designed using Verilog HDL, simulated and validated on Vertex-5 FPGA development board. From the results obtained from novel S-Box and BWMC techniques there is an improvement in terms of delay i.e. 73.1% as compared with hamming codes and 69% improvement in speed as compared with MC’s[22].
Keyword: AES, BWMC, ECC, Point Addition, Point Doubling, FPGA, Security System and S-Box.
Scope of the Article: Cryptography and Applied Mathematics