<?xml version="1.0" encoding="UTF-8"?>
<doi_batch version="4.3.0" xmlns="http://www.crossref.org/doi_resources_schema/4.3.0" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.crossref.org/doi_resources_schema/4.3.0 http://www.crossref.org/schema/deposit/doi_resources4.3.0.xsd">
<head>
<doi_batch_id>2522279d-7535-4a4f-9f01-b95235d6f20c</doi_batch_id>
<depositor>
<name>beie</name>
<email_address>director@blueeyesintelligence.org</email_address>
</depositor>
</head>
<body>
<doi_citations>
<doi>10.35940/ijitee.E8660.0310521</doi>
<citation_list><citation key="ref0"><doi>10.1109/TVLSI.2009.2022531</doi><unstructured_citation>Swaroop Ghosh, &quot;Voltage Scalable High-Speed Robust Hybrid Arithmetic Units Using Adaptive Clocking&quot;, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 18, No. 9, Sept. 2010, pp. 1301-1309.</unstructured_citation></citation><citation key="ref1"><doi>10.1109/TVLSI.2017.2724600</doi><unstructured_citation>Aurangozeb, &quot;Time-Domain Arithmetic Logic Unit with Built-In Interconnect&quot;, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 25, Iss. 10, Oct. 2017, pp. 2828 - 2841.</unstructured_citation></citation><citation key="ref2"><doi>10.1109/TCSII.2018.2873797</doi><unstructured_citation>Shahram Babaie, &quot;Design of an efficient Multilayer Arithmetic Logic Unit in Quantum-dot Cellular Automata (QCA)&quot;, IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 66, Iss. 6, June 2019, pp. 963 - 967.</unstructured_citation></citation><citation key="ref3"><doi>10.1049/iet-cds.2018.0046</doi><unstructured_citation>Medina-Santiago, &quot;Reconfigurable arithmetic logic unit designed with threshold logic gates&quot;, IET Circuits, Devices &amp; Systems, Vol. 13, Iss. 1, 2019, pp. 21-30.</unstructured_citation></citation><citation key="ref4"><doi>10.1109/ACCESS.2019.2963727</doi><unstructured_citation>Prashanth Barla, &quot;A Novel Low Power and Reduced Transistor Count Magnetic Arithmetic Logic Unit Using Hybrid STT-MTJ/CMOS Circuit&quot;, IEEE Access, Vol. 8, 2020, pp. 6876-6889.</unstructured_citation></citation><citation key="ref5"><doi>10.1109/TC.2009.62</doi><unstructured_citation>Siavash Bayat-Sarmadi, &quot;Concurrent Error Detection in Finite-Field Arithmetic Operations Using Pipelined and Systolic Architectures&quot;, IEEE Transactions on Computers, Vol. 58, No. 11, Nov. 2009, pp. 1553-1567.</unstructured_citation></citation><citation key="ref6"><doi>10.1109/TLA.2010.5688085</doi><unstructured_citation>S. Carrillo, &quot;Design and Implementation of an Arithmetic Processing Unit Based on the Logarithmic Number System&quot;, IEEE Latin America Transactions, Vol. 8, No. 6, Dec. 2010, pp. 605-617.</unstructured_citation></citation><citation key="ref7"><doi>10.1109/TASC.2012.2229334</doi><unstructured_citation>Mikhail Dorojevets, &quot;8-Bit Asynchronous Sparse-Tree Superconductor RSFQ Arithmetic-Logic Unit with a Rich Set of Operations&quot;, IEEE Transactions on Applied Superconductivity, Vol. 23, No. 3, June 2013.</unstructured_citation></citation><citation key="ref8"><doi>10.1109/TASC.2010.2103918</doi><unstructured_citation>T. Filippov, &quot;8-Bit Asynchronous Wave-Pipelined RSFQ Arithmetic-Logic Unit&quot;, IEEE Transactions on Applied Superconductivity, Vol. 21, No. 3, June 2011, pp. 847-851.</unstructured_citation></citation><citation key="ref9"><doi>10.1109/TCAD.2009.2013998</doi><unstructured_citation>Omid Sarbishei, &quot;A Formal Approach for Debugging Arithmetic Circuits&quot;, IEEE Transactions on Computer-Aided Design of Integrated Circuits And Systems, Vol. 28, No. 5, May 2009, pp. 742-754.</unstructured_citation></citation><citation key="ref10"><doi>10.1049/iet-nbt.2014.0056</doi><unstructured_citation>Ankur Sarker, &quot;Design of a DNA-Based Reversible Arithmetic and Logic Unit&quot;,IET Nano biotechnology, Vol. 9, Iss. 4, 2015, pp. 226 - 238.</unstructured_citation></citation><citation key="ref11"><doi>10.1109/TC.2008.204</doi><unstructured_citation>Alexandru Fit-Florea, &quot;A Discrete Logarithm Number System for Integer Arithmetic Modulo 2k:Algorithms and Lookup Structures&quot;, IEEE Transactions on Computers, Vol. 58, No. 2, Feb. 2009, pp. 163-174.</unstructured_citation></citation><citation key="ref12"><doi>10.1109/TCSI.2015.2388839</doi><unstructured_citation>Botang Shao, &quot;Array-Based Approximate Arithmetic Computing: A General Model and Applications to Multiplier andSquarer Design&quot;, IEEE Transactions on Circuits And Systems, Vol. 62, No. 4, April 2015, pp. 1081-1090.</unstructured_citation></citation><citation key="ref13"><doi>10.1109/TASC.2015.2507125</doi><unstructured_citation>Guang-Ming Tang, &quot;4-bit Bit-Slice Arithmetic Logic Unit for 32-bit RSFQ Microprocessors&quot;, IEEE Transactions on Applied Superconductivity, Vol. 26, Iss. 1, Jan. 2016.</unstructured_citation></citation><citation key="ref14"><doi>10.1109/JLT.2011.2170209</doi><unstructured_citation>Sisir Kumar Garai, &quot;A Novel All-Optical Frequency-Encoded Method to Develop Arithmetic and Logic Unit (ALU) Using Semiconductor Optical Amplifiers&quot;, Journal of Light wave Technology, Vol. 29, No. 23, Dec. 2011, pp. 3506-3514.</unstructured_citation></citation><citation key="ref15"><doi>10.1109/TASC.2018.2799994</doi><unstructured_citation>Guang-Ming Tang, &quot;Logic Design of a 16-bit Bit-Slice Arithmetic Logic Unit for 32-/64-bit RSFQ Microprocessors&quot;, IEEE Transactions on Applied Superconductivity, Vol. 28, Iss. 4, June 2018.</unstructured_citation></citation><citation key="ref16"><doi>10.1109/TCSI.2008.919757</doi><unstructured_citation>Tung-Chou Chen, &quot;Arithmetic Unit for Finite Field GF (2m)&quot;, IEEE Transactions on Circuits and Systems, Vol. 55, No. 3, April 2008, pp. 828-837.</unstructured_citation></citation><citation key="ref17"><doi>10.1049/iet-cds.2014.0103</doi><unstructured_citation>Weng-Geng Ho, &quot;Low power sub-threshold asynchronous quasi-delay-insensitive 32-bit arithmetic and logic unit based on autonomous signal-validity half-buffer&quot;, IET Circuits Devices Syst., Vol. 9, Iss. 4, 2015, pp. 309-318.</unstructured_citation></citation><citation key="ref18"><doi>10.1109/TCSII.2007.896937</doi><unstructured_citation>Mauro Olivieri, &quot;Analysis and Implementation of a Novel Leading Zero Anticipation Algorithm for Floating-Point Arithmetic Units&quot;, IEEE Transactions on Circuits And Systems, Vol. 54, No. 8, Aug. 2007, pp. 685-689.</unstructured_citation></citation><citation key="ref19"><doi>10.1109/TASC.2019.2904484</doi><unstructured_citation>F. Kirichenko, &quot;ERSFQ 8-bit Parallel Arithmetic Logic Unit&quot;, IEEE Transactions on Applied Superconductivity, Vol. 29, Iss. 5, Aug. 2019.</unstructured_citation></citation><citation key="ref20"><doi>10.1109/TCAD.2008.2003280</doi><unstructured_citation>Ajay K. Verma, &quot;Data-Flow Transformations to Maximize the Use of Carry-Save Representation in Arithmetic Circuits&quot;, IEEE Transactions on Computer-Aided Design of Integrated Circuits And Systems, Vol. 27, No. 10, Oct. 2008, pp. 1761-1774.</unstructured_citation></citation><citation key="ref21"><doi>10.1109/TNANO.2015.2504841</doi><unstructured_citation>Yuanfan Yang, &quot;Complementary Resistive Switch Based Arithmetic Logic Implementations Using Material Implication&quot;, IEEE Transactions on Nanotechnology, Vol. 15, Iss. 1, Jan. 2016, pp. 94-108.</unstructured_citation></citation><citation key="ref22"><doi>10.1049/iet-cds:20060036</doi><unstructured_citation>T. Basu, &quot;Arithmetic logic unit of a computer based on Spin-polarized single electrons&quot;, IET Circuits Devices Syst., Vol. 1, Iss. 3, 2007, pp. 194-199.</unstructured_citation></citation><citation key="ref23"><doi>10.1109/TC.2007.1071</doi><unstructured_citation>Kazuo Sakiyama, &quot;Multicore Curve-Based Cryptoprocessor with Reconfigurable Modular Arithmetic Logic Units over GF(2n)&quot;, IEEE Transactions on Computers, Vol. 56, No. 9, Sept. 2007, pp. 1269-1282.</unstructured_citation></citation><citation key="ref24"><doi>10.1109/TCAD.2007.906465</doi><unstructured_citation>Salvador Manich, &quot;Minimizing Test Time in Arithmetic Test-Pattern Generators With Constrained Memory Resources&quot;, IEEE Transactions on Computer-Aided Design of Integrated Circuits And Systems, Vol. 26, No. 11, Nov. 2007, pp. 2046-2058.</unstructured_citation></citation><citation key="ref25"><doi>10.1109/TC.2007.1073</doi><unstructured_citation>Shobha Vasudevan, &quot;Automatic Verification of Arithmetic Circuits in RTL Using Stepwise Refinement of Term Rewriting Systems&quot;, IEEE Transactions on Computers, Vol. 56, No. 10, Oct. 2007, PP. 1401-1414.</unstructured_citation></citation></citation_list>
</doi_citations>
</body>
</doi_batch>
