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<doi_batch version="4.4.2" xmlns="http://www.crossref.org/schema/4.4.2" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:jats="http://www.ncbi.nlm.nih.gov/JATS1" xsi:schemaLocation="http://www.crossref.org/schema/4.4.2 http://www.crossref.org/schema/deposit/crossref4.4.2.xsd">
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<doi_batch_id>-5171ffc0182b6af927f-473d</doi_batch_id>
<timestamp>20221008032242488</timestamp>
<depositor>
  <depositor_name>beie:beie</depositor_name> 
  <email_address>director@blueeyesintelligence.org</email_address>
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<registrant>WEB-FORM</registrant> 
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<journal>
<journal_metadata>   <full_title>International Journal of Innovative Technology and Exploring Engineering</full_title>   <abbrev_title>IJITEE</abbrev_title>   <issn media_type='electronic'>22783075</issn>   <doi_data>     <doi>10.35940/ijitee</doi>     <resource>https://www.ijitee.org/</resource>   </doi_data> </journal_metadata> <journal_issue>  <publication_date media_type='online'>     <month>10</month>     <day>30</day>     <year>2022</year>   </publication_date>   <journal_volume>     <volume>11</volume>   </journal_volume>   <issue>11</issue> </journal_issue> <!-- ============== --> <journal_article publication_type='full_text'>   <titles>     <title>IP Source Lockdown to Detect and Mitigate Multi-Destination, Multi-Port, Multi-Protocol DDoS Attacks in SDN</title> </titles>   <contributors>      <organization sequence='first' contributor_role='author'>Department of Computer Engineering, Devi Ahilya Vishwavidyala, Indore (M.P), India.</organization>    <person_name sequence='first' contributor_role='author'>      <given_name>Jitendra</given_name>      <surname>Patil</surname>    </person_name>    <person_name sequence='additional' contributor_role='author'>       <given_name>Vrinda</given_name>       <surname>Tokekar</surname>     </person_name>     <organization sequence='additional' contributor_role='author'>Professor, Department of Information Technology, Institute of Engineering and Technology, Devi Ahilya University. Indore (M.P), India.</organization>     <person_name sequence='additional' contributor_role='author'>       <given_name>Alpana</given_name>       <surname>Rajan</surname>     </person_name>     <organization sequence='additional' contributor_role='author'>Department of Computer Engineering, Devi Ahilya Vishwavidyala, Indore (M.P), India.</organization>   </contributors>     <jats:abstract xml:lang='en'>         <jats:p>Distributed Denial of Service (DDoS) attack is not a new attack and remains a challenging task. It has already been addressed by researchers and a lot of work has been done in this direction. Most of the work in Software-Defined-Network (SDN) environment focused on legacy DDoS attacks where targets are end servers. Legacy DDoS attack traffics are associated with a single destination and mostly the solutions are around this characteristic. In the case of SDN, the target is SDN controller plane whose overcharging brings the network to a complete halt. An attacker can achieve this by customizing Multi-Destination, Multi-Port, Multi-Protocol DDoS (MMMD) attack traffic to force the data plane to push more messages to the controller plane. In this paper, we have considered MMMD attack traffic which is just like normal traffic but has the potential to paralyze the complete SDN based networking infrastructure. In the contribution of this work, we have created MMMD traffic and proposed a model named “Simple, Lightweight DDoS Detection and Mitigation model in Software Defined Network” (SLDDM) to combat MMMD traffic in the SDN environment. SLDDM is based on the implementation of IP source-lockdown in SDN environment to detect and mitigate malicious traffic originating from spoof/legitimate IPs. The proposed model has been evaluated under different scenarios and compared with standard models in the literature. SLDDM brings down average response time in establishing https connections by legitimate hosts under attack scenario from 31 seconds to 0.054 seconds. It has been evaluated that the SLDDM keeps the SDN controller healthy and responsive to legitimate hosts under attack conditions.</jats:p>     </jats:abstract>  <publication_date media_type='online'>     <month>10</month>     <day>30</day>     <year>2022</year>   </publication_date>   <pages>     <first_page>29</first_page>     <last_page>40</last_page>   </pages>   <crossmark>     <crossmark_version>CC BY-NC-ND 4.0</crossmark_version>     <crossmark_policy>10.35940/BEIESP.CrossMarkPolicy</crossmark_policy>     <crossmark_domains>       <crossmark_domain>          <domain>www.ijitee.org</domain>       </crossmark_domain>     </crossmark_domains>     <crossmark_domain_exclusive>true</crossmark_domain_exclusive>   </crossmark>   <doi_data>     <doi>10.35940/ijitee.K9295.10111122</doi>     <resource>https://www.ijitee.org/portfolio-item/k929510111122/</resource>   </doi_data> </journal_article><!-- ============== --> <journal_article publication_type='full_text'>   <titles>     <title>Local Oscillator Phase Noise Impact on M-ary Modulation Schemes</title>   </titles>   <contributors>      <organization sequence='first' contributor_role='author'>DEETC, Instituto Superior de Engenharia de Lisboa and Centre of Technology and Systems, Lisbon, Portugal.</organization>    <person_name sequence='first' contributor_role='author'>      <given_name>Vitor</given_name>      <surname>Fialho</surname>    </person_name>    <person_name sequence='additional' contributor_role='author'>       <given_name>Fernando</given_name>       <surname>Fortes</surname>     </person_name>     <organization sequence='additional' contributor_role='author'>DEETC, Instituto Superior de Engenharia de Lisboa and Instituto de Telecomunicações, Lisbon, Portugal. </organization>   </contributors>    <jats:abstract xml:lang='en'>         <jats:p>This paper presents the impact of a local oscillator phase noise on digital modulation schemes based on bit error rate and error vector magnitude. The adopted methodology enables base band metrics estimation which is dependent of a specific communication standard. A generic local oscillator phase noise model is presented to evaluate the impact of different phase noise values on error vector magnitude and bit error rate. For a phase noise of -65dBc @ 1kHz the error vector magnitude changes from 7% to 12.8%. Increasing the modulation order leads to bit error rate increment for the same phase noise value.</jats:p>     </jats:abstract>  <publication_date media_type='online'>     <month>10</month>     <day>30</day>     <year>2022</year>   </publication_date>   <pages>     <first_page>41</first_page>     <last_page>46</last_page>   </pages>   <crossmark>     <crossmark_version>CC BY-NC-ND 4.0</crossmark_version>     <crossmark_policy>10.35940/BEIESP.CrossMarkPolicy</crossmark_policy>     <crossmark_domains>       <crossmark_domain>          <domain>www.ijitee.org</domain>       </crossmark_domain>     </crossmark_domains>     <crossmark_domain_exclusive>true</crossmark_domain_exclusive>   </crossmark>   <doi_data>     <doi>10.35940/ijitee.K9302.10111122</doi>     <resource>https://www.ijitee.org/portfolio-item/k930210111122/</resource>   </doi_data> </journal_article>
</journal>
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