e8fd940a-9852-4f99-82c8-124eefc7ad00 beie director@blueeyesintelligence.org 10.35940/ijitee.L9321.11111222 10.1109/TED.2018.2874047W. Li and J. C. S. Woo, "Optimization and Scaling of Ge-Pocket TFET," in IEEE Transactions on Electron Devices, vol. 65, no. 12, pp. 5289-5294[CrossRef]10.1109/LED.2007.901273W. Y. Choi, B. -G. Park, J. D. Lee and T. -J. K. Liu, "Tunneling Field-Effect Transistors (TFETs) With Subthreshold Swing (SS) Less Than 60 mV/dec," in IEEE Electron Device Letters, vol. 28, no. 8, pp. 743-745[CrossRef]10.1109/TED.2010.2040661Bardon, Marie Garcia et al. "Pseudo-Two-Dimensional Model for Double-Gate Tunnel FETs Considering the Junctions Depletion Regions." IEEE Transactions on Electron Devices, vol. 57, 2010, pp: 827-834.[CrossRef]Cao J (2017) Ph.D. dissertation, Université Grenoble Alpes, France10.1080/21681724.2019.1600729Aadil T. Shora & Farooq A. Khanday, Quasi-analytical model-based performance analysis of dual material gate stack strained GAA FinFET, International Journal of Electronics Letters, vol.8, 2020, no.3, pp. 304-318[CrossRef]10.1109/TED.2013.2284503N. Fasarakis, T. Karatsori, A. Tsormpatzoglou, D.Tassis ,Compact Modeling of Nanoscale Trapezoidal FinFETs. IEEE Transactions on Electron Devices, vol 61, no.2, 2014, pp:324-332.[CrossRef]10.1088/1674-4926/39/12/124016Aadil T. Shora and Farooq A. Khanday, 3D modelling based comprehensive analysis of high-κ gate stack graded channel dual material trigate MOSFET, Journal of Semiconductors, vol. 39, no. 12, pp.:124016[CrossRef]10.1049/iet-cds.2018.5302Aadil Tahir Shora, Farooq A. Khanday, Analytical modelling and performance analysis of gate- and channel-engineered trapezoidal trigate MOSFET, IET Circuits Devices Syst., vol.13, 2019, pp.: 1107-1116.[CrossRef]10.1007/s12633-019-00163-zSaha, R., Bhowmick, B. & Baishya, S. Impact of Mole Fractions due to Work Function Variability (WFV) of Metal Gate on Electrical Parameters in Strained SOI-FinFET. Silicon, vol. 12,2020, pp. 577-583.[CrossRef]10.1109/MELCON.2008.4618555W. G. Vandenberghe, A. S. Verhulst, G. Groeseneken, B. Soree and W. Magnus, "Analytical model for a tunnel field-effect transistor," MELECON 2008 - The 14th IEEE Mediterranean Electrotechnical Conference, 2008, pp. 923-928[CrossRef]10.1007/s10825-016-0843-0Saeid Marjani, Seyed Ebrahim Hosseini, and Rahim Faez. 2016. A 3D analytical modeling of tri-gate tunneling field-effect transistors. J. Comput. Electron. Vol.15, 2016, No. 3, pp. 820-830.[CrossRef]10.1109/16.19942K. K. Young, "Short-channel effect in fully depleted SOI MOSFETs," in IEEE Transactions on Electron Devices, vol. 36, no. 2, pp. 399-402.[CrossRef]10.1002/jnm.2571AT.Shora, FA. Khanday, FA, Three-dimensional analytical modeling and performance analysis of triple material trigate silicon-on-insulator MOSFET. Int J Numer Model. 2019; vol. 32:e2571.[CrossRef]Atlas User's Manual, SILVACO Int., Santa Clara, CA, USA, Aug. 2016.