<?xml version="1.0" encoding="UTF-8"?>
<doi_batch version="4.3.0" xmlns="http://www.crossref.org/doi_resources_schema/4.3.0" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.crossref.org/doi_resources_schema/4.3.0 http://www.crossref.org/schema/deposit/doi_resources4.3.0.xsd">
<head>
<doi_batch_id>150f12a8-5462-4901-bde2-bb8a16fb5f7a</doi_batch_id>
<depositor>
<name>beie</name>
<email_address>director@blueeyesintelligence.org</email_address>
</depositor>
</head>
<body>
<doi_citations>
<doi>10.35940/ijitee.E9848.0411522</doi>
<citation_list><citation key="ref0"><doi>10.1109/4.192043</doi><unstructured_citation>Fang Lu, &quot;A 200-MHz CMOS Pipelined Multiplier-Accumulator Using a Quasi-Domino Dynamic Full- Adder Cell Design&quot;, IEEE Journal of Solid-State Circuits, Vol. 28, No. 2, Feb. 1993, pp.123 - 132.</unstructured_citation></citation><citation key="ref1"><doi>10.1109/4.494202</doi><unstructured_citation>Robert Rogenmoser, &quot;An 800-MHz 1-pm CMOS Pipelined 8-b Adder Using True Single-phase Clocked Logic-Flip-Flops&quot;, IEEE Journal of Solid-State Circuits, Vol. 31, No. 3, March. 1996, pp. 401 - 409.</unstructured_citation></citation><citation key="ref2"><doi>10.1109/CJECE.2003.1426068</doi><unstructured_citation>Arash Shoarinejad, &quot;Low-power single-bit full adder cells Cellules d'addition complete 1-bit ' a faible puissance&quot;, Vol. 28, No. 1, Jan. 2003.</unstructured_citation></citation><citation key="ref3"><doi>10.1109/TASC.2021.3091963</doi><unstructured_citation>Haolin Cong, &quot;An 8-b Multiplier Using Single-Stage Full Adder Cell in Single-Flux-Quantum Circuit Technology&quot;, IEEE Transactions on Applied Superconductivity , Vol. 31, Iss. 6, Sept. 2021.</unstructured_citation></citation><citation key="ref4"><doi>10.1109/TED.2018.2866048</doi><unstructured_citation>Zhuo-Rui Wang, &quot;Efficient Implementation of Boolean and Full-Adder Functions With 1T1R RRAMs for Beyond von Neumann In-Memory Computing&quot;, IEEE Transactions on Electron Devices, Vol. 65, Iss.10, Oct. 2018 pp. 4659 - 4666.</unstructured_citation></citation><citation key="ref5"><doi>10.1109/TMAG.2013.2245911</doi><unstructured_citation>Erya Deng, &quot;Low Power Magnetic Full-Adder Based on Spin Transfer Torque MRAM&quot;, IEEE Transactions on Magnetics, Vol. 49, No. 9, Sept. 2013, pp. 4982 - 4987.</unstructured_citation></citation><citation key="ref6"><doi>10.1109/TCSII.2019.2899938</doi><unstructured_citation>Sally Ahmed, &quot;A Compact Adder and Reprogrammable Logic Gate Using Micro-electromechanical Resonators with Partial Electrodes&quot;, IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 66, Iss. 12, Dec. 2019, pp. 2057 - 2061.</unstructured_citation></citation><citation key="ref7"><doi>10.1109/TVLSI.2014.2353058</doi><unstructured_citation>Chang-Joon Park, &quot;Efficient Broadband Current-Mode Adder Quantizer Design for Continuous-Time Sigma-Delta Modulators&quot;, IEEE Transactions on Very Large-Scale Integration (VLSI) Systems, Vol. 23, Iss. 9, Sept. 2015, pp. 1920 - 1930.</unstructured_citation></citation><citation key="ref8"><doi>10.1109/TVLSI.2014.2357057</doi><unstructured_citation>Partha Bhattacharyya, &quot;Performance Analysis of a Low-Power High-Speed Hybrid 1-bit Full Adder Circuit&quot;, IEEE Transactions On Very Large Scale Integration (VLSI) Systems, Vol. 23, Iss. 10, Oct. 2015, pp. 2001 - 2008.</unstructured_citation></citation><citation key="ref9"><doi>10.1109/4.509867</doi><unstructured_citation>Kiniio Ueda, &quot;A 64-bit Carry Look Ahead Adder Using Pass Transistor BICMOS Gates&quot;, IEEE Journal of Solid-State Circuits, Vol. 31. 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</doi_citations>
</body>
</doi_batch>
