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<citation_list><citation key="ref0"><doi>10.1109/TVLSI.2017.2750207</doi><unstructured_citation>Giuseppe Scotti, &quot;Design of Low-Voltage High-Speed CML D-Latches in Nanometer CMOS Technologies&quot;, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 25, Iss. 12, Dec. 2017, pp. 3509 - 3520.</unstructured_citation></citation><citation key="ref1"><doi>10.1109/JSSC.2005.845994</doi><unstructured_citation>Yongsam Moon, &quot;A Divide-by-16.5 Circuit for 10-Gb Ethernet Transceiver in 0.13µm CMOS&quot;, IEEE Journal of Solid-State Circuits, Vol. 40, No. 5, May 2005, pp. 1175-1179.</unstructured_citation></citation><citation key="ref2"><doi>10.1109/4.90071</doi><unstructured_citation>M. Afghahi, &quot;Double Edge-Triggered D-Flip-Flops for High-speed CMOS Circuits&quot;, IEEE Journal of Solid-State Circuits, Vol. 26, No. 8, Aug.1991, pp. 1168-1170.</unstructured_citation></citation><citation key="ref3"><doi>10.1109/4.340421</doi><unstructured_citation>Masataka Matsui, &quot;A 200 MHz 13 mm2 2-D DCT Macrocell Using Sense Amplifying Pipeline Flip-Flop Scheme&quot;, IEEE Journal of Solid-State Circuits, Vol. 29, No. 12. Dec. 1994, pp. 1482-1490.</unstructured_citation></citation><citation key="ref4"><doi>10.1109/JSSC.2016.2625341</doi><unstructured_citation>Sang-Geun Bae, &quot;3-Gb/s High-Speed True Random Number Generator Using Common-Mode Operating Comparator and Sampling Uncertainty of D Flip-Flop&quot;, IEEE Journal of Solid-State Circuits, Vol. 52, Iss. 2, Feb. 2017, pp. 605 - 610.</unstructured_citation></citation><citation key="ref5"><doi>10.1109/4.720406</doi><unstructured_citation>Ching-Yuan Yang, &quot;New Dynamic Flip-Flops for High-Speed Dual-Modulus Prescaler&quot;, IEEE Journal of Solid-State Circuits, Vol. 33, No. 10, Oct. 1998, pp. 1568-1571.</unstructured_citation></citation><citation key="ref6"><doi>10.1109/4.482195</doi><unstructured_citation>Jan Craninckx, &quot;A 1 .8-GHz CMOS Low-Phase-Noise Voltage-Controlled Oscillator with Prescaler&quot;, IEEE Journal of Solid-State Circuits, Vol. 30, No. 12, Dec. 1995, pp. 1474-1482.</unstructured_citation></citation><citation key="ref7"><doi>10.1109/4.509860</doi><unstructured_citation>Byungsoo Chang, &quot;A 1.2 GHz CMOS Dual-Modulus Prescaler Using New Dynamic D-Type Flip-Flops&quot;, IEEE Journal of Solid-State Circuits, Vol. 31, No. 5, May 1996, pp. 749-752.</unstructured_citation></citation><citation key="ref8"><doi>10.1109/TCSI.2002.800837</doi><unstructured_citation>Pradeep Varma, &quot;A MOS Approach to CMOS DET Flip-Flop Design&quot;, IEEE Transactions on Circuits and Systems-I: Fundamental Theory and Applications, Vol. 49, No. 7, July 2002, pp. 1013-1016.</unstructured_citation></citation><citation key="ref9"><doi>10.1109/TCSI.2013.2295026</doi><unstructured_citation>Djaafar Chabi, &quot;Ultra Low Power Magnetic Flip-Flop Based on Checkpointing/Power Gating and Self-Enable Mechanisms&quot;, IEEE Transactions on Circuits and Systems-I: Regular Papers, Vol. 61, No. 6, June 2014, pp. 1755-1765.</unstructured_citation></citation><citation key="ref10"><doi>10.1109/TNS.2009.2031972</doi><unstructured_citation>David L. Hansen, &quot;Clock, Flip-Flop, and Combinatorial Logic Contributions to the SEU Cross Section in 90 nm ASIC Technology&quot;, IEEE Transactions on Nuclear Science, Vol. 56, No. 6, Dec. 2009, pp. 3542-3550.</unstructured_citation></citation><citation key="ref11"><doi>10.1109/15.350243</doi><unstructured_citation>R. E. Wallace, &quot;Fast-Transient Susceptibility of a D-Type Flip-Flop&quot;, IEEE Transactions on Electromagnetic Compatability. Vol. 31, No. 1, Feb. 1995, pp. 75-80.</unstructured_citation></citation><citation key="ref12"><doi>10.1109/TNS.2010.2073486</doi><unstructured_citation>Slawosz Uznanski, &quot;Monte-Carlo Based Charge Sharing Investigations on a Bulk 65 nm RHBD Flip-Flop&quot;, IEEE Transactions on Nuclear Science, Vol. 57, No. 6, Dec. 2010, pp. 3267-3272.</unstructured_citation></citation><citation key="ref13"><doi>10.1109/TNS.2010.2081687</doi><unstructured_citation>Balaji Narasimham, &quot;Contribution of Control Logic Upsets and Multi-Node Charge Collection to Flip-Flop SEU Cross-Section in 40-nm CMOS&quot;, IEEE Transactions on Nuclear Science, Vol. 57, No. 6, Dec. 2010, pp. 3176-3182.</unstructured_citation></citation><citation key="ref14"><doi>10.1109/TCSI.2021.3122340</doi><unstructured_citation>Parth Parekh, &quot;Improved Metastability of True Single-Phase Clock D-FlipflopsWith Applications in Vernier Time-to-Digital Converters&quot;, IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 69, Iss. 3, Mar. 2022, pp. 1102-1114.</unstructured_citation></citation><citation key="ref15"><doi>10.1109/TNS.2011.2170201</doi><unstructured_citation>S. Jagannathan, &quot;Single-Event Tolerant Flip-Flop Design in 40-nm Bulk CMOS Technology&quot;, IEEE Transactions on Nuclear Science, Vol. 58, No. 6, Dec. 2011, pp. 3033-3037.</unstructured_citation></citation><citation key="ref16"><doi>10.1109/TNS.2013.2273437</doi><unstructured_citation>K. Lilja, &quot;Single-Event Performance and Layout Optimization of Flip-Flops in a 28-nm Bulk Technology&quot;, IEEE Transactions on Nuclear Science, Vol. 60, No. 4, Aug. 2013, pp. 2782-2788.</unstructured_citation></citation><citation key="ref17"><doi>10.1109/TNS.2016.2636338</doi><unstructured_citation>Leqing Zhang, &quot;Single Event Upset Sensitivity of D-FlipFlop : Comparision of PDSOI with Bulk Si at 130nm Technology Node&quot;, IEEE Transactions on Nuclear Science, Vol. 64, Iss. 1, Jan. 2017, pp. 683 - 688.</unstructured_citation></citation><citation key="ref18"><unstructured_citation>R. M. Chen, &quot;Impact of Temporal Masking of Flip-Flop Upsets on Soft Error Rates of Sequential Circuits&quot;, IEEE Transactions on Nuclear Science, Vol. 64, Iss. 8, Aug. 2017, pp. 2098 - 2106.</unstructured_citation></citation><citation key="ref19"><doi>10.1109/JSSC.2002.807406</doi><unstructured_citation>Tsuneaki Fuse, &quot;A 0.5-V Power-Supply Scheme for Low-Power System LSIs Using Multi-Vth SOI CMOS Technology&quot;, IEEE Journal of Solid-State Circuits, Vol. 38, No. 2, Feb. 2003, pp. 303-311.</unstructured_citation></citation><citation key="ref20"><doi>10.1109/TVLSI.2012.2227850</doi><unstructured_citation>Ajay N. Bhoj, &quot;Design of Logic Gates and Flip-Flops in High-performance FinFET Technology&quot;, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 21, Iss. 11, Nov. 2013, pp. 1975 - 1988.</unstructured_citation></citation><citation key="ref21"><doi>10.1109/TCSII.2016.2531098</doi><unstructured_citation>Mahendra Sakare, &quot;Bandwidth enhancement of flip-flops using feedback for high-speed integrated circuits&quot;, IEEE Transactions on Circuits and Systems - Part II: Express Briefs, Vol. 63, Iss. 8, Aug. 2016, pp. 768 - 772.</unstructured_citation></citation><citation key="ref22"><doi>10.1109/TMAG.2016.2542790</doi><unstructured_citation>Hao Cai, &quot;Low Power Magnetic Flip-flop Optimization with FDSOI Technology Boost&quot;, IEEE Transactions on Magnetics, Vol. 52, Iss. 8, Aug. 2016.</unstructured_citation></citation><citation key="ref23"><doi>10.1109/TNANO.2015.2438017</doi><unstructured_citation>Hao Cai, &quot;Multiplexing Sense Amplifier Based Magnetic Flip-Flop in 28nm FDSOI Technology&quot;, IEEE Transactions on Nanotechnology, 2015.</unstructured_citation></citation></citation_list>
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