-4d90550d17f4602e089-5513 20220407070911876 beie:beie director@blueeyesintelligence.org WEB-FORM International Journal of Innovative Technology and Exploring Engineering IJITEE 22783075 10.35940/ijitee https://www.ijitee.org/ 04 30 2022 11 5 Department of Electronics and Communication Engineering, Vellore Institute of Technology, Tirupati (A. P) India. Pulipati Bhargav Uppalapati Dhanush Department of Electronics and Communication Engineering, Vellore Institute of Technology, Tirupati (A. P) India. Sb Mohammad Ansar Department of Electronics and Communication Engineering, Vellore Institute of Technology, Tirupati (A. P) India. This work provides us an efficient way of developing a motion controlled interaction with a computer or laptop without touching it. This is achieved by capturing motion using an external source and processing it to perform the action needed. This work can help a lot of people to save time as they don’t need to come over to perform the task and it can also help people who are physically challenged to use the computer as it is all about making hand moments and interacting with the computer. Our work is based on continuous hand picture acknowledgement framework. 04 30 2022 37 39 CC BY-NC-ND 4.0 10.35940/BEIESP.CrossMarkPolicy www.ijitee.org true 10.35940/ijitee.E9836.0411522 https://www.ijitee.org/portfolio-item/e98360411522/ Department of Electronics & Communication Engineering, Jawaharlal Nehru Technological University, Kakinada. Guntur (Andhra Pradesh), India. Soniya Nuthalapati Kusuma Nutalapati Department of Electronics & Communication Engineering, Jawaharlal Nehru Technological University, Kakinada. Guntur (Andhra Pradesh), India. Naveen Laghuvarapu Prasad Nagipogu Department of Electronics & Communication Engineering, Jawaharlal Nehru Technological University, Kakinada. Guntur (Andhra Pradesh), India. P. Yaswanth Sai Mandepudi Koteswararao Department of Electronics & Communication Engineering, Jawaharlal Nehru Technological University, Kakinada. Guntur (Andhra Pradesh), India. Maddineni Venkata Jaya Prakash Department of Electronics & Communication Engineering, Jawaharlal Nehru Technological University, Kakinada. Guntur (Andhra Pradesh), India. The impedance cardiography (ICG) shows the impedance caused in the heart. The ICG gives a clear and accurate results and the applied techniques reduce artifacts and also mathematical calculations. The ICG signal shows various physiological and non-physiological situations, and can calculate the heart volume. The computational complexity is also a main part for remote health care. The adaptive techniques used in this project reduces or removes the noise in the signal, Improve the signal. Mainly to take over the applied signal, convergence rate, and to reduce computations of the proposed theory, we added the sign and normalized adaptive algorithms to take out the realistic wave. In final, the results are taken out from the outcomes by additionally relating it with the adaptive filter to situate it in the proper format. 04 30 2022 16 20 CC BY-NC-ND 4.0 10.35940/BEIESP.CrossMarkPolicy www.ijitee.org true 10.35940/ijitee.E9847.0411522 https://www.ijitee.org/portfolio-item/e98470411522/ Department of Electronics & Communication Engineering, Jawaharlal Nehru Technological University, Kakinada. Guntur (Andhra Pradesh), India. Soniya Nuthalapati Ch. Jyothirmayi Department of Electronics & Communication Engineering, Jawaharlal Nehru Technological University, Kakinada. Guntur (Andhra Pradesh), India. Galla. Saikiran Department of Electronics & Communication Engineering, Jawaharlal Nehru Technological University, Kakinada. Guntur (Andhra Pradesh), India. Chaitanya Prathikonda Department of Electronics & Communication Engineering, Jawaharlal Nehru Technological University, Kakinada. Guntur (Andhra Pradesh), India. Arigala Joseph Jagarlamudi Manikanta Department of Electronics & Communication Engineering, Jawaharlal Nehru Technological University, Kakinada. Guntur (Andhra Pradesh), India. This project visualizes the different designs of Full Adder (FADDR) circuits. These FADDR circuits are designed mainly to reduce the power and delay factors. If these two factors are minimized then automatically the power delay product (PDP) gets minimized. In addition, to design the FADDR, we used multiplexer. So, that the FADDR transistor count gets reduced. Here in this FADDR implementation, it is designed with different transistors count and the factors like power consumption propagation delay and power delay product (PDP) constraints are tabulated with different transistor count of FADDR designs. Then the power consumption and propagation delay factors get reduced. The designs are simulated by using 45nm CMOS technology in Cadence Virtuoso tool. 04 30 2022 21 26 CC BY-NC-ND 4.0 10.35940/BEIESP.CrossMarkPolicy www.ijitee.org true 10.35940/ijitee.E9848.0411522 https://www.ijitee.org/portfolio-item/e98480411522/ Department of Electronics & Communication Engineering, Jawaharlal Nehru Technological University, Kakinada. Guntur (Andhra Pradesh), India. Dr. C. Arunabala P.V.Sai Ranjitha Department of Electronics & Communication Engineering, Jawaharlal Nehru Technological University, Kakinada. Guntur (Andhra Pradesh), India. Bomminayuni Likhitha Gunturu Sravya Department of Electronics & Communication Engineering, Jawaharlal Nehru Technological University, Kakinada. Guntur (Andhra Pradesh), India. Bonagiri Navyasree Department of Electronics & Communication Engineering, Jawaharlal Nehru Technological University, Kakinada. Guntur (Andhra Pradesh), India. Arumalla Mounika Department of Electronics & Communication Engineering, Jawaharlal Nehru Technological University, Kakinada. Guntur (Andhra Pradesh), India. At Present, portable battery-operated devices are enhancing due to low power consumption and high-speed applications, The designed circuit with feedback are used to design novel circuits. If the comparator having feedback are without clock signal. The comparators are mainly designed to minimize the power consumption and with good accuracy because of clock signal, if the clock signal is there, it is used to drive the circuit with low current. But in the existed design the circuit is with high power and current. These drawbacks are overcome by using the projected designed comparator. The Projected comparator design is with reduced power consumption, propagation delay, currents and with a smaller number of transistors. The comparators are useful in analog to digital converters. And this is simulated by using 45 nm CMOS technology Cadence Virtuoso tool. 04 30 2022 27 31 CC BY-NC-ND 4.0 10.35940/BEIESP.CrossMarkPolicy www.ijitee.org true 10.35940/ijitee.E9849.0411522 https://www.ijitee.org/portfolio-item/e98490411522/ Department of Electronics & Communication Engineering, Jawaharlal Nehru Technological University, Kakinada. Guntur (Andhra Pradesh), India. Dr. C. Arunabala A. Lohithakshi Department of Electronics & Communication Engineering, Jawaharlal Nehru Technological University, Kakinada. Guntur (Andhra Pradesh), India. D. Jyothsna Department of Electronics & Communication Engineering, Jawaharlal Nehru Technological University, Kakinada. Guntur (Andhra Pradesh), India. CH. Pranathi Department of Electronics & Communication Engineering, Jawaharlal Nehru Technological University, Kakinada. Guntur (Andhra Pradesh), India. A. Navaneetha Department of Electronics & Communication Engineering, Jawaharlal Nehru Technological University, Kakinada. Guntur (Andhra Pradesh), India. This Project details about the design of D Flip Flop (DFPFP). This D Flip Flop circuit is analyzed by using the supply voltage level methods. These methods are used mainly to suppress the power consumption caused due to leakage currents. In addition, because of this implemented technique, the time taken for battery backup, and the supply voltage given at standby mode gets minimized. The projected circuit uses a smaller number of transistors, such that power consumption and leakage currents are in prior limit. Mainly, the CMOS D Flip Flops are designed to use them in binary counters, shift registers, Analog and Digital circuit designs. And this circuit design is implemented in 45nm CMOS Technology Cadence Virtuoso Tool. 04 30 2022 32 36 CC BY-NC-ND 4.0 10.35940/BEIESP.CrossMarkPolicy www.ijitee.org true 10.35940/ijitee.E9850.0411522 https://www.ijitee.org/portfolio-item/e98500411522/