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<citation_list><citation key="ref0"><doi>10.1587/transele.E95.C.710</doi><unstructured_citation>A. Fathi, S. Azizian, K. Hadidi, and A. Khoei, &quot;A novel and very fast 4-2 compressor for high-speed arithmetic operations,&quot; IEICE Trans. Electron., vols. E95, no. 4, pp. 710-712, 2012. [CrossRef]</unstructured_citation></citation><citation key="ref1"><doi>10.1109/4.540066</doi><unstructured_citation>I. S. Abu-Khater, A. Bellaouar, and M. I. Elmasry, &quot;Circuit techniques for CMOS low-power high-performance multipliers,&quot; IEEE J. Solid-State Circuits, vol. 31, no. 10, pp. 1535-1546, Oct. 1996. [CrossRef]</unstructured_citation></citation><citation key="ref2"><unstructured_citation>O. Kwon, K. Nowka, and E. E. Swartzlander, &quot;A 16-bit × 16-bit MAC design using fast 5:2 compressors,&quot; in Proc. IEEE Int. Conf. Appl.- Specific Syst., Archit., Processors, Jul. 2000, pp. 235-243.</unstructured_citation></citation><citation key="ref3"><doi>10.1109/12.863039</doi><unstructured_citation>W.-C. Yeh and C.-W. Jen, &quot;High-speed booth encoded parallel multiplier design,&quot; IEEE Trans. Comput., vol. 49, no. 7, pp. 692-701, Jul. 2000. [CrossRef]</unstructured_citation></citation><citation key="ref4"><doi>10.1109/92.988727</doi><unstructured_citation>A. M. Shams, T. K. Darwish, and M. A. Bayoumi, &quot;Performance analysis of low-power 1-bit CMOS full adder cells,&quot; IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 10, no. 1, pp. 20-29, Feb. 2002. [CrossRef]</unstructured_citation></citation><citation key="ref5"><doi>10.1109/4.84935</doi><unstructured_citation>P. J. Song and G. De Micheli, &quot;Circuit and architecture trade-offs for high-speed multiplication,&quot; IEEE J. Solid-State Circuits, vol. 26, no. 9, pp. 1184-1198, Sep. 1991. [CrossRef]</unstructured_citation></citation><citation key="ref6"><doi>10.1109/12.485568</doi><unstructured_citation>V. G. Oklobdzija, D. Villeger, and S. S. Liu, &quot;A method for speed optimized partial product reduction and generation of fast parallel multipliers using an algorithmic approach,&quot; IEEE Trans. Comput., vol. 45, no. 3, pp. 294-306, Mar. 1996. [CrossRef]</unstructured_citation></citation><citation key="ref7"><doi>10.1109/TCSI.2004.835683</doi><unstructured_citation>C.-H. Chang, J. Gu, and M. Zhang, &quot;Ultra-low-voltage low-power CMOS 4-2 and 5-2 compressors for fast arithmetic circuits,&quot; IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 51, no. 10, pp. 1985-1997, Oct. 2004. [CrossRef]</unstructured_citation></citation><citation key="ref8"><doi>10.1109/ISCAS.2012.6271526</doi><unstructured_citation>A. Fathi, S. Azizian, K. Hadidi, A. Khoei, and A. Chegeni, &quot;CMOS implementation of a fast 4-2 compressor for parallel accumulations,&quot; in Proc. IEEE Int. Symp. Circuits Syst., May 2012, pp. 1476-1479. [CrossRef]</unstructured_citation></citation><citation key="ref9"><doi>10.1109/ACSSC.2001.986892</doi><unstructured_citation>K. Prasad and K. K. Parhi, &quot;Low-power 4-2 and 5-2 compressors,&quot; in Proc. Conf. Rec. 25th Asilomar Conf. Signals, Syst. Comput., Nov. 2001, pp. 129-133. [CrossRef]</unstructured_citation></citation><citation key="ref10"><doi>10.1109/ISMS.2016.87</doi><unstructured_citation>P. Saha, P. Samanta, and D. Kumar, &quot;4:2 and 5:2 decimal compressors,&quot; in Proc. 7th Int. Conf. Intell. Syst., Modelling Simulation (ISMS), Jan. 2016, pp. 424-429 [CrossRef]</unstructured_citation></citation><citation key="ref11"><doi>10.1049/el.2017.3339</doi><unstructured_citation>D. Balobas and N. Konofaos, &quot;Low-power high-performance CMOS 5-2 compressor with 58 transistors,&quot; Electron. Lett., vol. 54, no. 5, pp. 278-280, Mar. 2018. [CrossRef]</unstructured_citation></citation><citation key="ref12"><doi>10.1109/MIPRO.2014.6859537</doi><unstructured_citation>A. Najafi, S. Timarchi, and A. Najafi, &quot;High-speed energy-efficient 5:2 compressor,&quot; in Proc. 37th Int. Conv. Inf. Commun. Technol., Electron. Microelectron., Opatija, Croatia, May 2014, pp. 80-84. [CrossRef]</unstructured_citation></citation><citation key="ref13"><unstructured_citation>M. Tohidi, M. Mousazadeh, S. Akbari, K. Hadidi, and A. Khoei, &quot;CMOS implementation of a new high speed, glitch-free 5-2 compressor for fast arithmetic operations,&quot; in Proc. 20th Int. Conf. Mixed Design Integr. Circuits Syst. (MIXDES), Jun. 2013, pp. 204-208.</unstructured_citation></citation><citation key="ref14"><doi>10.1109/ICECS.2010.5724442</doi><unstructured_citation>G. Caruso and D. Di Sclafani, &quot;Analysis of compressor architectures in MOS current-mode logic,&quot; in Proc. 17th IEEE Int. Conf. Electron., Circuits Syst., Dec. 2010, pp. 13-16. [CrossRef]</unstructured_citation></citation><citation key="ref15"><unstructured_citation>W. Ma and S. Li, &quot;A new high compression compressor for the large multiplier,&quot; in Proc. 9th Int. Conf. Solid-State Integrated-Circuit Technol., Oct. 2008, pp. 1877-1880.</unstructured_citation></citation><citation key="ref16"><doi>10.1109/AICCSA.2007.370924</doi><unstructured_citation>M. Rouholamini, O. Kavehie, A.-P. Mirbaha, S. J. Jasbi, and K. Navi, &quot;A new design for 7:2 compressors,&quot; in Proc. IEEE/ACS Int. Conf. Comput. Syst. Appl. (AICCSA), May 2007, pp. 474-478. [CrossRef]</unstructured_citation></citation><citation key="ref17"><doi>10.7763/IJMO.2013.V3.314</doi><unstructured_citation>S. Mehrabi, K. Navi, and O. Hashemipour, &quot;Performance comparison of high-speed high-order (n:2) and (n:3) CNFET-based compressors,&quot; Int. J. Model. Optim., vol. 3, no. 5, pp. 432-435, Oct. 2013. [CrossRef]</unstructured_citation></citation><citation key="ref18"><unstructured_citation>C. Pan, Z. Wang, and C. Sechen, &quot;High speed and power efficient compression of partial products and vectors,&quot; J. Algorithms Optim., Oct., vol. 1, no. 1, pp. 39-54, 2013.</unstructured_citation></citation><citation key="ref19"><unstructured_citation>G. Yang, S.-O. Jung, K.-H. Baek, S. Hwan Kim, S. Kim, and S.-M. Kang, &quot;A 32-bit carry-lookahead adder using dual-path all-N logic,&quot; IEEE Trans. Very Larg.</unstructured_citation></citation></citation_list>
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