<?xml version="1.0" encoding="UTF-8"?>
<doi_batch version="4.4.2" xmlns="http://www.crossref.org/schema/4.4.2" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:jats="http://www.ncbi.nlm.nih.gov/JATS1" xsi:schemaLocation="http://www.crossref.org/schema/4.4.2 http://www.crossref.org/schema/deposit/crossref4.4.2.xsd">
<head>
<doi_batch_id>-3bf97310184a13a8c1e5ef</doi_batch_id>
<timestamp>20230303044833676</timestamp>
<depositor>
  <depositor_name>beie:beie</depositor_name> 
  <email_address>director@blueeyesintelligence.org</email_address>
</depositor>
<registrant>WEB-FORM</registrant> 
</head>
<body>
<journal>
<journal_metadata>   <full_title>International Journal of Innovative Technology and Exploring Engineering</full_title>   <abbrev_title>IJITEE</abbrev_title>   <issn media_type='electronic'>22783075</issn>   <doi_data>     <doi>10.35940/ijitee</doi>     <resource>https://www.ijitee.org/</resource>   </doi_data> </journal_metadata> <journal_issue>  <publication_date media_type='online'>     <month>03</month>     <day>30</day>     <year>2023</year>   </publication_date>   <journal_volume>     <volume>12</volume>   </journal_volume>   <issue>4</issue> </journal_issue><!-- ============== --> <journal_article publication_type='full_text'>   <titles>     <title>Delay-Optimistic Multiplier Design using Parallel Prefix Adder with Compressors</title>   </titles>   <contributors>      <organization sequence='first' contributor_role='author'>Principal and Professor, Vardhaman College of Engineering, Hyderabad (Telangana), India.</organization>    <person_name sequence='first' contributor_role='author'>      <given_name>Dr. J.V.R.</given_name>      <surname>Ravindra</surname>      <ORCID>https://orcid.org/0000-0001-7636-1791</ORCID>    </person_name>    <person_name sequence='additional' contributor_role='author'>       <given_name>Chava</given_name>       <surname>Chaitanya</surname>       <ORCID>https://orcid.org/0009-0006-8937-8537</ORCID>     </person_name>     <organization sequence='additional' contributor_role='author'>Department of Electronics and Communication Engineering, Vardhaman College of Engineering, Hyderabad (Telangana), India.</organization>     <person_name sequence='additional' contributor_role='author'>       <given_name>Kasam</given_name>       <surname>Pranya</surname>       <ORCID>https://orcid.org/0009-0000-4399-0903</ORCID>     </person_name>     <organization sequence='additional' contributor_role='author'>Department of Electronics and Communication Engineering, Vardhaman College of Engineering, Hyderabad (Telangana), India.</organization>     <person_name sequence='additional' contributor_role='author'>       <given_name>Vaddem</given_name>       <surname>Sahiti</surname>       <ORCID>https://orcid.org/0009-0003-3275-6435</ORCID>     </person_name>     <organization sequence='additional' contributor_role='author'>Department of Electronics and Communication Engineering, Vardhaman College of Engineering, Hyderabad (Telangana), India.</organization>   </contributors>    <jats:abstract xml:lang='en'>         <jats:p>This article provides an illustration of the design process for 5-2 and 7-2 compressors operating at extremely high speeds. When compared to the prior designs, the new approach significantly reduced the gate-level delay while maintaining an appropriate overall transistor and gate count. With the help of 7:2 and 5:2 compressor infusion, when compared to earlier designs, the gate-level latency has been significantly decreased while the overall transistor and gate counts have remained within acceptable bounds. The technique was created for the 5-2 compressor and expanded for the 7-2 design, which exhibits higher speed performance enhancement for these architectures. To increase performance in terms of latency, we can switch out the ripple carry adder at the last addition for a parallel prefix adder. In addition, careful design considerations were taken to keep other factors, such as power and activity, within reasonable bounds. The best-reported circuits have also undergone redesigns, and the parasitic components of those circuits have been eliminated using the same method to produce a fair comparison. Using a common 16 × 16-bit multiplier, the performance of the built compressor blocks has also been assessed.</jats:p>     </jats:abstract>  <publication_date media_type='online'>     <month>03</month>     <day>30</day>     <year>2023</year>   </publication_date>   <pages>     <first_page>8</first_page>     <last_page>14</last_page>   </pages>   <crossmark>     <crossmark_version>CC BY-NC-ND 4.0</crossmark_version>     <crossmark_policy>10.35940/BEIESP.CrossMarkPolicy</crossmark_policy>     <crossmark_domains>       <crossmark_domain>          <domain>www.ijitee.org</domain>       </crossmark_domain>     </crossmark_domains>     <crossmark_domain_exclusive>true</crossmark_domain_exclusive>     <custom_metadata>       <assertion explanation='Funding' group_label='Funding' group_name='Funding' name='Declaration' order='0'>The institution provides a licenced version of Xilinx for this project's development.</assertion>       <assertion explanation='Conflicts of Interest' group_label='Conflicts of Interest' group_name='Conflicts-of-Interest' name='Declaration' order='1'>To the best of our knowledge, there are no conflicts of interest.</assertion>       <assertion explanation='Ethical Approval and Consent to Participate' group_label='Ethical Approval and Consent to Participate' group_name='Ethical-Approval-and-Consent-to-Participate' name='Declaration' order='2'>No, the article does not require ethical approval and consent to participate with evidence.</assertion>       <assertion explanation='Availability of Data and Material' group_label='Availability of Data and Material' group_name='Availability-of-Data-and-Material' name='Declaration' order='3'>Yes, It is relevant. Most of the data is collected from different papers and journals as mentioned in references.</assertion>       <assertion explanation='Authors Contributions' group_label='Authors Contributions' group_name='Authors-Contributions' name='Declaration' order='4'>All authors have equal participation in this article.</assertion>     </custom_metadata>   </crossmark>   <doi_data>     <doi>10.35940/ijitee.D9475.0312423</doi>     <resource>https://www.ijitee.org/portfolio-item/D94750312423/</resource>   </doi_data> </journal_article>
</journal>
</body>
</doi_batch>
