FPGA Implementation of Booth’s and Baugh-Wooley Multiplier using Verilog
Manish Chaudhary1, Mandeep Singh Narula2

1Manish Chaudhary, Department of ECE, ITM University, Gurgaon (Haryana), India.
2Mandeep Singh Narula, Assistant Professor, Department of ECE, ITM University, Gurgaon (Haryana), India.
Manuscript received on 11 June 2013 | Revised Manuscript received on 17 June 2013 | Manuscript Published on 30 June 2013 | PP: 221-224 | Volume-3 Issue-1, June 2013 | Retrieval Number: A0918063113/13©BEIESP
Open Access | Editorial and Publishing Policies | Cite | Mendeley | Indexing and Abstracting
© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: Here, in this paper we have designed and implemented a Signed-Unsigned Booth’s Multiplier and a Signed-Unsigned Baugh-Wooley Multiplier for 32-bits multiplication. The designing and verification is done through verilog on Xilinx 12.4. In this paper we tried to explain the step by step process that was adopted for Signed-Unsigned Booth’s Multiplier. Also, two different approaches for implementing the Signed Baugh-Wooley multiplier in Singed-Unsigned Baugh-Wooley multiplier and after, the implementation we could see the differences in certain parameters. The array structure of Signed-Unsigned Booth’s Multiplier and Signed-Unsigned Baugh-Wooley Multiplier is obtained from RTL synthesis are shown. Different parameters like power, CPU usage, CPU time, memory usage etc. have been compared.
Keywords: Array, Booth, Baugh-Wooley, Signed, Unsigned, Verilog.

Scope of the Article: FPGAs