Design and Implementaion of Energy Efficient Muliplier Architecture in Low POWER Vlsi
Rajendra Prasad
Dr. Rajendra Prasad, Assistant Professor, Department of Electronics and Communication Engineering, Malla Reddy Engineering College, Secunderabad, Telangana, India.
Manuscript received on 01 December 2018 | Revised Manuscript received on 06 December 2018 | Manuscript Published on 26 December 2018 | PP: 18-22 | Volume-8 Issue- 2S2 December 2018 | Retrieval Number: BS2002128218/19©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open-access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: The Low power multipliers having high clock frequencies assume a significant role in the present advanced technology. Multiplier is such a vital component which subsidises the aggregate power utilization in a systematic environment. Low Power VLSI optimization is carried out from basic subsystem level to architecture level. Power reduction is addressed at every stage of design thus the overall power reduction is minimized. Various innovative design techniques namely, clock gating, power gating and low power libraries are adopted to minimize power dissipation. The techniques proposed in this publication can be generalized and adopted for design complex signal processing and communication blocks required for various applications. To estimate 2’s complement of multiplicand for final Partial Product Row (PPRG) we used MBE technique in proposed system. The proposed multiplier consumes power up to 60% and reduce the logic delay up to 7.2% and route delay up to 92%. So compared to all existed multipliers, the proposed multiplier produces effective results.
Keywords: Low Power Multipliers, Digital Signal Processing, Power Reduction Techniques, High Clock Frequencies, Modified Booth Encoding (MBE), Partial Product Row Generation (PPRG).
Scope of the Article: Communication