FPGA Implementation of Efficient Hardware for the Advanced Encryption Standard
Amandeep Kaur1, Puneet Bhardwaj2, Naveen Kumar3
1Amandeep Kaur, Department of Electronics and Communication, Thapar University, Patiala (Punjab), India.
2Puneet Bhardwaj, Department of Electronics and Communication, Thapar University, Patiala (Punjab), India.
3Naveen Kumar, Department of Electronics and Communication, Thapar University, Patiala (Punjab), India.
Manuscript received on 07 February 2013 | Revised Manuscript received on 21 February 2013 | Manuscript Published on 28 February 2013 | PP: 187-190 | Volume-2 Issue-3, February 2013 | Retrieval Number: C0463022313/2013©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: We present an efficient hardware architecture design & implementation of Advanced Encryption Standard (AES) – Rijndael cryptosystem. The AES algorithm defined by the National Institute of Standard and Technology (NIST) of United States has been widely accepted. All the cryptographic algorithms developed can be implemented with software or built with pure hardware. However with the help of Field Programmable Gate Arrays (FPGA) we tend to find expeditious solution and which can be easily upgraded to integrateany concordat changes. This contribution investigates the AES encryption and decryption cryptosystem with regard to FPGA and Very High Speed Integrated Circuit Hardware Description language (VHDL). Optimized and Synthesizable VHDL code is developed for the implementation of both 128-bit data encryption and decryption process. Xilinx ISE 10.1 software is used for simulation. Each program is tested with some of the sample vectors provided by NIST and output results are perfect with minimal delay. The synthesis results found from FPGA implementation by Xilinx Synthesis Tool on Virtex II pro kit shows that the computation time for generating the ciphertext by AES with 4 sbox and 2 dual port RAM is 6.922 ns.
Keywords: Cryptography, Advanced Encryption Standard, Rijndael, S-box, Key Expansion, Cipher Text.
Scope of the Article: FPGAs