High Speed and Gate at 22nm Metal Gate Strained Silicon Technology
Shobha Sharma1, Ashwani Kumar2, Nupur Prakash3, B.V.R. Reddy4
1Ashwani Kumar, Department of ECE, Indira Gandhi Delhi Technical University, Women (Delhi), India.
2Nupur Prakash, Department of ECE, Indira Gandhi Delhi Technical University, Women (Delhi), India.
3B.V.R. Reddy, Department of ECE, Indira Gandhi Delhi Technical University, Women (Delhi), India.
4Shobha Sharma, Department of ECE, Indira Gandhi Delhi Technical University, Women (Delhi), India.
Manuscript received on 8 August 2013 | Revised Manuscript received on 18 August 2013 | Manuscript Published on 30 August 2013 | PP: 24-25 | Volume-3 Issue-3, August 2013 | Retrieval Number: C1073083313/13©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: This paper demonstrates a high speed AND gate at 22nm High K metal gate Strained Silicon making use of forward body biasing. The simulations are done with hspice simulator with ‘HP ptm’ models of Arizona State University, USA. Forward body biasing results in higher speed with shortened propagation time on an average and ‘on an average’ shortened rise time and fall time. There is deterioration of output voltage if static forward body biasing is beyond a limit. The output voltage levels can be at its best inspite of the forward body biasing with the use of different circuit configuration, which is a future scope of this research paper. Also the other side effects of forward body biasing can be overcome with new techniques The average decrease in rise time and fall time is 4 % and average decrease in propagation delay is 39 % for input low to output low and 13% for input high to output high.
Keywords: 22nm, High Speed AND Gate, CMOS AND Gate, Forward Body Biasing, Hi K Metal Gate Strained Si, Ptm Models.
Scope of the Article: High Speed Networks