A Hybrid and Memory Efficient Multiplier and Accumulator Design Using Radix -4 Algorithm
Sagar Krishna Sivvam1, Solomon Gotham2
1Sagar Sivam, M.Tech ECE Department, JNTU Kakinada University, Kaushik College of Engineering, Visakhapatnam, India.
2Solomon Gotham, Professor & Head, Dept. of ECE, Kaushik College of Engineering, visakhapatnam, India.
Manuscript received on October 01, 2012. | Revised Manuscript received on October 20, 2012. | Manuscript Published on September 10, 2012. | PP: 40-43 | Volume-1 Issue-4, September 2012. | Retrieval Number: D0247081412/2012©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: In this paper we proposed a new architecture for high speed MAC operation. By combining multiplication and addition and devising a hybrid type of Carry save adder, the performance was improved. The proposed CSA uses 1’s complement based radix-2 booth algorithm The multiplication and accumulation unit provides high speed multiplication along with accumulative addition. And for final addition some final such as CLA, Kogge stone adder and then adders compare their performance characteristics. The one most effective way to increase the speed of a multiplier is to reduce the number of the partial products. Although the number of partial products can be reduced with a higher radix booth encoder, but the number of hard multiples that are expensive to generate also increases simultaneously. To increase the speed and performance, many parallel MAC architectures have been proposed. The design was implemented on Xilinx Xc3s500E fpga and the device utilized 13% of the total LUT’s and the total power utilization was 0.041mW.
Keywords: Radix-4 Booth multiplier, CLA, multiplier and- accumulator (MAC).