High Performance Low Power Dynamic Multiplier
Vagolu Aruna1, P. Deepthi2

1Aruna Vagolu, Department of ECE, Pydah College of Engineering and Technology, (Andhra Pradesh), India.
2P.Deepthi, Associate Professor, Department of ECE, Pydah College of Engineering and Technology, (Andhra Pradesh), India.
Manuscript received on 12 October 2013 | Revised Manuscript received on 20 October 2013 | Manuscript Published on 30 October 2013 | PP: 116-118 | Volume-3 Issue-5, October 2013 | Retrieval Number: E1255103513/13©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: The DPST has been applied on both the modified Booth decoder and the compression tree of multipliers to enlarge the power reduction. This paper provides the experience of applying an advanced version of our former dynamic power suppression technique (DPST) on multipliers for high-speed and low-power purposes. To filter out the use-less switching power, there are two approaches, i.e., using registers and using AND gates, to assert the data signals of multipliers after the data transition. The simulation results show that the DPST implementation with AND gates owns an extremely high flexibility on adjusting the data asserting time which not only facilitates the robustness of DPST but also leads to a 40% speed improvement. Adopting a Xilinx Spartan 3 Xc3s200 board the proposed DPST-equipped multiplier dissipates only 0.0121 mW per MHz in H.264 texture coding applications, and obtains a 40% power reduction and the overall utilization of the resources reduced to 26%.
Keywords: (DPST), AND, H.264.

Scope of the Article: High Speed Networks