Design & Optimization of CNTFET based Low Power Schmitt Trigger using MTCMOS Technique
Yogesh Giri Goswami1, Nikhil Saxena2
1Yogesh Giri Goswami, Department of Electronics and Communication Engineering, ITM University Multidisciplinary, Gwalior, Madhya Pradesh, India.
2Nikhil Saxena, Department of Electronics and Communication Engineering, ITM University Multidisciplinary, Gwalior, Madhya Pradesh, India.
Manuscript received on 05 April 2019 | Revised Manuscript received on 14 April 2019 | Manuscript Published on 24 May 2019 | PP: 247-252 | Volume-8 Issue-6S3 April 2019 | Retrieval Number: F10500486S319/19©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open-access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Power consumption to be reduced is a critical burden for any circuits reduced in portable electronic gadgets to improve battery for long life has put mandatory friction to construct low power circuit. MTCMOS technique gives two sleep mode transistors in current circuits are engage to reduce power consumption. In this proposed work is to construct powerless Schmitt trigger using MTCMOS technique in 32nm both on CMOS and CNTFET Schmitt trigger. The proposed Schmitt trigger circuit to be improved in terms of leakage, hysteresis loss and propagation delay for CMOS and CNTFET Schmitt trigger has been done by MTCMOS technique in 1V supply. The proposed design is simulated using SPICE tool in 32nm technology node. After simulation it is established that results give a notable reduction in leakage power or hysteresis loss for current design. Leakage power offers by MTCMOS approach in CNTFET based technology are 2pW and hysteresis loss 17mV at 1V power supply.
Keywords: CMOS, CNTFET, MTCMOS, Schmitt Trigger.
Scope of the Article: Communication