Advanced Rail Clamping PWM Techniques based Three Level VSI fed DTC Induction Motor Drive for THD and Common Mode Voltage Reduction
C. Harinatha Reddy1, K. SriGowri2, T. Brahmananda Reddy3, A.Pradeep Kumar Yadav4

1C. Harinatha Reddy, Associate Professor, Department of Electrical and Electronics Engineering, G. Pulla Reddy Engineering College, Kurnool, Andhra Pradesh, India.

2K. SriGowri, Professor, Department of Electrical and Electronics Engineering, G. Pulla Reddy Engineering College, Kurnool, Andhra Pradesh, India.

3T. Brahmananda Associate Professor, Department of Electrical and Electronics Engineering, G. Pulla Reddy Engineering College, Kurnool, Andhra Pradesh, India.

4A. Pradeep Kumar Yadav, Assistant Professor, Department of Electrical and Electronics Engineering, G. Pulla Reddy Engineering College, Kurnool, Andhra Pradesh, India.

Manuscript received on 08 April 2019 | Revised Manuscript received on 15 April 2019 | Manuscript Published on 24 May 2019 | PP: 645-652 | Volume-8 Issue-6S3 April 2019 | Retrieval Number: F11290486S319/19©BEIESP

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Abstract: A space vector approach to advanced rail clamping pulse width modulation methods (ARCPWM) is developed to integrate direct torque control (DTC) scheme for the speed control of a three level inverter fed induction motor. In this method the behavior of different ARCPWM methods is analyzed with respect to zero state variation. It is observed that ARCPWM3 shows reduction in both current harmonics as well as the common mode voltage (CMV) during near rated speed operation of the drive. To validate the proposed method a generalized ARCPWM (GARCPWM) program is developed to generate various ARCPWM methods using a constant variable ‘k’ that facilitates the instant of variation of zero state. Simulations results for various ARCPWM controlled three level inverter fed DTC induction motor drive are presented for comparing the performance in terms of total harmonic distortion of motor currents and CMV.

Keywords: ARCPWM, CMV, DTC, GARCPWM.
Scope of the Article: Computer Architecture and VLSI