Low Power, Low Phase Noise Based Phase Locked Loop and its Design Implementations
Shubham1, Sakthivel R2

1Shubham, Department of Micro and Nanoelectronics, Engineering, Vellore Institute of Technology, Vellore (Tamil Nadu), India.
2Sakthivel R, Department of Micro and Nanoelectronics, Engineering, Vellore Institute of Technology, Vellore (Tamil Nadu), India.
Manuscript received on 07 April 2019 | Revised Manuscript received on 20 April 2019 | Manuscript published on 30 April 2019 | PP: 1139-1143 | Volume-8 Issue-6, April 2019 | Retrieval Number: F3721048619/19©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: In this work, we have discussed a new approach in designing the phase-locked loop (PLL), the proposed circuit is designed with the GDI cell-based PFD, charge pump and low pass filter. For frequency matching and for larger locking state, the design used as D flipflop from the TSMC library. It is used as frequency synthesizers and divides the incoming frequency by 2.This design uses 5 stage current starved voltage control oscillator (CS-VCO). The designed PFD is free from the dead zone issue and it is suitable for the low power applications. the designed PLL works for an average frequency range of 8 GHz and its offset frequency is targeted at 1GHz.This PLL model has low phase noise of -112 dBc/Hz at 1 Mhz frequency which is quite standard and the power consumption of the circuit is 8 µW. The entire work is simulated using Cadence Virtuoso 45 nm Technology.
Keyword: Charge Pump, FD, PLL. PFD, Phase Locked Loop.
Scope of the Article: Low-power design