Modified Han Carlson Adder Based Multiply Accumulate Unit for Low Power Digital Signal Processor
Rakesh S1, K. S. Vijula Grace2
1Rakesh S, Department of Electronics and Communication Engineering, Noorul Islam Centre for Higher Education, Thuckalay, (Tamil Nadu), India.
2K.S. Vijula Grace, Department of Electronics and Communication Engineering, Noorul Islam Centre for Higher Education, Thuckalay (Tamil Nadu), India.
Manuscript received on 07 April 2019 | Revised Manuscript received on 20 April 2019 | Manuscript published on 30 April 2019 | PP: 1144-1148 | Volume-8 Issue-6, April 2019 | Retrieval Number: F3725048619/19©BEIESP
Open Access | Ethics and Policies | Cite | Mendeley | Indexing and Abstracting
© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: The aim of this work is to propose a novel architecture for implementing Multiply Accumulate (MAC) unit which can be used to build a power efficient Digital Signal Processor (DSP). The proposed method uses hybrid parallel prefix adder in the multiplier stage and in the adder stage. The method improves the power consumption as well as the power-delay product. In the proposed architecture, a Han Carlson adder with modified pre-processing and post-processing stages (HCA_MPPS) is used in the Vedic multiplier and in the adder stage. The units are designed using Verilog Hardware Description Language (HDL) and simulated and synthesized for Artix-7 series Field Programmable Gate Array (FPGA) using Xilinx Vivado Design Suite 2015.2. The analysis showed that the proposed design has significant improvement in the power consumption and the figure of merit (power-delay product). The MAC unit employing modified Han Carlson adder has given a power saving of 11.38% and showed an improvement of 6.36% in the power-delay product.
Keyword: Digital Signal Processor, Han Carlson Adder, Modified Inequality Detector, Multiply Accumulate Unit, Vivado Design Suite.
Scope of the Article: Digital Signal Processing Theory