Verification of Analog & Mixed Signal Ips Using Sv-Uvm Methodology
Subhranshu Shekhar Padhee1, Anil Arora2
1Subhranshu Shekhar Padhee, Pursuing Bvvbvn M. Tech, Degree in VLSI Design Stream Thapar Institute of Engineering and Technology, Patiala (Punjab), India.
2Dr.Anil Arora, Assistant Professor, at Thapar Institute of Engineering, and Technology, Patiala (Punjab), India.
Manuscript received on 01 May 2019 | Revised Manuscript received on 15 May 2019 | Manuscript published on 30 May 2019 | PP: 1541-1543 | Volume-8 Issue-7, May 2019 | Retrieval Number: G5928058719/19©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: UVM Based methodology (UVM) is one of the broadly utilized check system to upgrade the confirmation nature of Simple and Complex IPs Configuration so as to accelerate the check procedure. A check situation to confirm the usefulness of IP by utilizing Framework in System Verilog – UVM based methodology. Simulator used to check the Complex IPs was Cadence Incisive. With the proper test plan and verification plan verification of IPs became easier. Analog and mixed signal IP structure are among the fastest developing need and market demand. Most frameworks on-chip (SoC) plans today are complex and mixed signal .The main goal of this project is to Verify the Functionality of Analog IPs like LDOs and the Functional Coverage.
Keyword: Universal Verification Methodology, LDOs, Self-Checking Test Bench.
Scope of the Article: Signal and Image Processing.