Enhancement of Short Channel Effect and Drain Induced Barrier Lowering in Fin-FET
Jagtap Sarika Madhukar1, Gond Vitthal Janardan2

1Ms. Jagtap Sarika Madhukar, Assistant Professor E & TC Department Nashik District Maratha Vidya Prasarak Samaj’s Karmaveer Adv. Baburao Ganpatrao Thakare College of Engineering.
2Dr. Gond Vitthal Janardan, Professor, E & TC Department, MET’s Institute of Engineering Bhujbal Knowledge City, Nashik.
Manuscript received on April 20, 2020. | Revised Manuscript received on April 30, 2020. | Manuscript published on May 10, 2020. | PP: 1303-1308 | Volume-9 Issue-7, May 2020. | Retrieval Number: G6007059720/2020©BEIESP | DOI: 10.35940/ijitee.G6007.059720
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: The essential requirement of any battery-operated and mobile devices like laptops, cellular phones are that they must be small in size, consume less power, fast processing and cheaper expansion. Gordon Moore found in 1965 that the quantity of transistors on a chip will drive to be twofold every year, by manufacturing the portable devices and building circuit on the silicon chip which makes device cost effective. This drop in size of transistor is termed as scaling. Since scaling faces formidable challenges in nanometer regime, successors have been emerged as Fin FET’s. They have thin fin or wing like channels enclosed by several gates. Due to many gates the design helps to improve performance and boost energy efficacy. Present work highlights the role of scaling and how scaling improves the speed of the device. The expectation from the scaled device is to consume as low power as possible, effective in costs and less design time. As we make the instrument more portable, complexity in it becomes infinite. Moore’s law supports us to realize the role of scaling to improve circuit performance and make a portable/mobile device. Here, we design 14nm, 10nm and 7nm Triple gate Fin-FET (TG Fin-FET) and investigate the Drain Induced Barrier Lowering (DIBL) and Short Channel Effect (SCE). By scaling the device DIBL and SCE are reduced giving better performance in terms of power and speed. 
Keywords: BSIM, Fin-FET, Modeling, Mos FET.
Scope of the Article: Numerical Modelling of Structures