Design and Implementation of Reduced DC-link Capacitance using Voltage Compensation Technique for a Solar PV Module
K. Usha1, S. Manasa2, R. Priyadharshini3

1K.Usha, Associate Professor, Department of Electrical and Electronics Engineering, SSN College of Engineering, Anna University, Chennai (Tamil Nadu), India.
2S.Manasa, UG Scholar, Department of Electrical and Electronics Engineering, SSN College of Engineering, Anna University, Chennai (Tamil Nadu), India.
3R.Priyadharshini, UG Scholar, Department of Electrical and Electronics Engineering, SSN College of Engineering, Anna University, Chennai (Tamil Nadu), India.

Manuscript received on 01 May 2019 | Revised Manuscript received on 15 May 2019 | Manuscript published on 30 May 2019 | PP: 1882-1885 | Volume-8 Issue-7, May 2019 | Retrieval Number: G6208058719/19©BEIESP
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Abstract: The bulkiness of the DC link capacitor is a very critical matter of concern, in the solar power harnessing circuit. An alternative method to reduce this bulk capacitor is necessary to reduce the overall cost of the system and the ripple content in the circuit, without affecting the overall efficiency of the system. In this paper, a methodology is proposed in which a voltage compensator is integrated with the DC bus line to accomplish the reduction in the DC link capacitance for a solar PV module.
Keyword: DC Link Capacitor, Voltage Compensator, Capacitor Reduction.
Scope of the Article: Microstrip Antenna Design and Application.