High Performance VLSI Architecture for Braun Multiplier
S. Karunakaran1, B. Poonguzharselvi2

1S.Karunakaran, Department of ECE, Vardhaman College of Engineering, Shamshabad, Hyderabad-501218, India.
2B.Poonguzharselvi, Department of CSE, Chaitanya Bharathi Institute of Technology, Gandipet, Hyderabad-500075, India.

Manuscript received on 02 July 2019 | Revised Manuscript received on 09 July 2019 | Manuscript published on 30 August 2019 | PP: 362-365 | Volume-8 Issue-10, August 2019 | Retrieval Number: I8326078919/2019©BEIESP | DOI: 10.35940/ijitee.I8326.0881019
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: The requirement for portable devices with high fidelity should consume less power . Adding two binary numbers is the basic thing in ALU Unit. Adder is an important part of the processor. The complexity of designing the multiplier and ALU changes due to the transistor count. Full adder plays a vital role in signal processing applications, Embedded systems. In the design of fundamental computation units such as multiplier should be included in future applications. Designing VLSI multipliers helps in deriving high end performance architecture which minimizes the consumed power consumption in the architecture. Generally, parallel multipliers are adopted for area optimization and processing speed. 28 T and 20 T full adders are designed which is further utilized for the implementation of Braun multiplier in virtuso schematic of Cadence software 180nm transistor size design.
Keywords: Braun multiplier, 3 bit adder, low power
Scope of the Article: Computer Architecture and VLSI