Design And Analysis of RHBD Memory Cells And 4×4 RHBD 10T Memory Cell Architecture
M. Chaitanya1, V. Kannan2
1M. Chaitanya, PG Scholar, Department of Goods Movement Reference Institute of Technology, India.
2V. Kannan, Professor, Department of Engineering and Communication Engineering, GMRIT, Rajam, India.

Manuscript received on 01 August 2019 | Revised Manuscript received on 05 August 2019 | Manuscript published on 30 August 2019 | PP: 4232-4237 | Volume-8 Issue-10, August 2019 | Retrieval Number: J99460881019/19©BEIESP | DOI: 10.35940/ijitee.J9946.0881019
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Abstract: CMOS technology plays an important role in the modern electronics world. CMOS technology also plays significant role in aerospace applications. To store data, memories are widely used as the medium in aerospace applications. SRAM cells are the memories made by the CMOS technology. The most vital issues faced by memories are due to single event upsets (SEUs) which are induced by radiation particles. The SEU’s due to increase in densities and SEU’s. There is a decrease in critical charge and supply voltage in CMOS process technology. There is a need for a technique which can to tolerate these SEU’s in such aerospace applications. Which are in the environment of complex celestial radiation? The technique which is considered for such environment is radiation-hardened by design (RHBD) with soft error robustness. This paper aims at is proposing an area efficient and high reliable RHBD memory cell for the above said application using 45nm technology in Cadence Tool. Depending on power, write/read time, the layout area of 14T, 12T and 10T RHBD memory cells and their performance on power for read/write operations are observed. A comparative study is also done on these memory cells based the parameters considered.
Keywords: Architecture, CMOS, RHBD.

Scope of the Article: Network Architectures