Design of Efficient SOC Bus Based on WISHBONE
Bharath S.V1, Ashwini S. Shivannavar2, M. Z. Kurian3
1Mr. Bharath S.V, Department of E&C, SSIT, Tumkur (Karnataka), India.
2Mrs. Ashwini S. Shivannavar, Department of E&C, SSIT, Tumkur (Karnataka), India.
3Dr. M. Z. Kurian, Department of E&C, SSIT, Tumkur (Karnataka), India.
Manuscript received on 11 June 2013 | Revised Manuscript received on 17 June 2013 | Manuscript Published on 30 June 2013 | PP: 112-115 | Volume-3 Issue-1, June 2013 | Retrieval Number: A0902063113/13©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: In this paper wishbone bus is used to interconnect variety of devices. SOC designs are usually based on FPGA and ASIC which are widely used in embedded systems. In SOC design flexible interconnection between variety of devices is crucial to get maximum performance. Usually, in SOC design variety of devices such as high performance units like CPU, DMA, RAM ext., low performance devices like UART, GPIO’s are connected to a single bus. The interconnecting bus runs at the speed of low speed device. An extra logic needs to be used in SOC to increase the performance of low speed devices, but this increases overall system power consumption. This paper proposes double bus architecture to interconnect the different devices according to the speed of the devices. High speed devices are connected to first level wishbone bus and low speed devices are connected to second level bus. This architecture shows that double bus design is feasible in low power SOC design.
Keywords: Double Bus, IP Core, SOC, Wishbone.
Scope of the Article: Aspect-Based Software Engineering