FPGA Implementation of MPLS
Mirza Raheber Raza1, Praveen Kumar Y. G2, M. Z. Kurian3, K.V. Narayanswamy4

1Mirza Raheber Raza, PG Student, Sri Siddhartha Institute of Technology, Tunkur (Karnataka), India.
2Praveen Kumar Y.G, Lecturer, Department of E&C, Sri Siddhartha Institute of Technology, Tunkur (Karnataka), India.
3Dr. M. Z. Kurian, Hod and Professor, Department of E&C, Sri Siddhartha Institute of Technology, Tunkur (Karnataka), India.
4Dr. K. V. Narayanswamy, Professor, Department of E&E, MS Ramaiah School of Advanced Studies, Bangalore (Karnataka), India.
Manuscript received on 11 June 2013 | Revised Manuscript received on 17 June 2013 | Manuscript Published on 30 June 2013 | PP: 120-122 | Volume-3 Issue-1, June 2013 | Retrieval Number: A0908063113/13©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: This paper presents a hardware architecture of Multi-Protocol Label Switching (MPLS). MPLS is a protocol used primarily to prioritize internet traffic and improve bandwidth utilization. MPLS solutions are meant to be used with Layer 2 or Layer 3 protocols. This paper presents hardware architecture to implement MPLS on FPGA.
Keywords: Bandwidth, FPGA, Internet Traffic, MPLS.

Scope of the Article: FPGAs