Implementation of VLSI Architecture for Montgomery Modular Multiplier
Shobana Priya M S1, Priyanka R2, Manikandan T3, Joshua Kumaresan S4, Satheesh Kumar S5

1M. S. Shobana Priya, M.E., Ph.D, Assistant Professor, Department of ECE, Saveetha School of Engineering, India.

2R. Priyanka, M.E., Ph.D, Assistant Professor, Department of ECE, Saveetha School of Engineering, India.

3Dr. T. Manikandan, Professor, Department of ECE, Rajalakshmi Engineering College, Chennai (Tamil Nadu), India.

4Dr. S. Joshua Kumaresan, Associate Professor, Department of ECE, R.M.K. Engineering College, (Tamil Nadu), India.

5S. Satheesh Kumar, Assistant Professor, Department of ECE, Sri Krishna College of Engineering and Technology, Coimbatore (Tamil Nadu), India.

Manuscript received on 23 November 2019 | Revised Manuscript received on 04 December 2019 | Manuscript Published on 14 December 2019 | PP: 218-221 | Volume-9 Issue-1S November 2019 | Retrieval Number: A10451191S19/2019©BEIESP | DOI: 10.35940/ijitee.A1045.1191S19

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Abstract: The paper proposes a Montgomery Modular Multiplier (MMM) using a simple and efficient Montgomery multiplication algorithm. Here a modification in the form of using hybrid full adders in the Carry Save adder is proposed. The hybrid full adder is designed using a conventional Complementary Metal Oxide Semiconductor and transmission gate logic. There is about 54% and 55% reduction of area (no. of components) in Radix 2 MMM and Semi-Carry-Save (SCS) based MMM with hybrid full adders. There is significant reduction in the power dissipation of 52% for Radix 2 MMM and 46% of SCS based MMM when hybrid adders are used instead of C-CMOS Full-Adders. The delay is also reduced by 47% in SCS based MMM as compared to that of Radix 2 MMM. The software used are Xilinx ISE 14.2 and Mentor Graphics Pyxis Schematic in 180-nm technology.

Keywords: MMM, C-CMOS, SCS, Hybrid Full Adder.
Scope of the Article: Computer Architecture and VLSI