SPI Implementation on FPGA
Trupti D. Shingare1, R. T. Patil2

1Ms.Trupti, M.Tech(Digital System)-II, R.I.T. Rajaramnagar, Sakhrale, Islampur, Maharashtra.
2Prof. Mr. R. T. Patil, Associate Professor, Department of E & Tc, R.I.T. Sakhrale, Islampur, Maharashtra.
Manuscript received on 09 January 2013 | Revised Manuscript received on 18 January 2013 | Manuscript Published on 30 January 2013 | PP: 7-9 | Volume-2 Issue-2, January 2013 | Retrieval Number: B0350012213 /2013©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: The SPI is a full-duplex, synchronous, serial data link that enables communication between a host processor and peripherals. Based upon Motorola’s SPI-bus specifications, version V03.06, release February 2003, the designs are general purpose solutions offering viable ways to controlling SPI-bus, and highly flexible to suit any particular needs. However, Field programmable gate array devices offer a quicker and more customizable solution. This paper provides a full description of an up to- date SPI Master/Slave FPGA implementations, In conformity with design-reuse methodology.
Keywords: Serial Peripheral Interface (SPI), Field Programmable Gate Array (FPGA), System on Chip (SOC)

Scope of the Article: FPGAs