Implementation of Vedic Multiplier and Floating Point Matrix Multiplier in Image Compression Applications
T. Amy Prasanna

T. Amy Prasanna, Professor, Department of Electrical and Electronics Engineering, Malla Reddy College of Engineering for Women, (Telangana), India. 

Manuscript received on 22 December 2020 | Revised Manuscript received on 12 January 2020 | Manuscript Published on 23 January 2020 | PP: 7-9 | Volume-9 Issue-2S5 December 2019 | Retrieval Number: B10021292S519/2019©BEIESP | DOI: 10.35940/ijitee.B1002.1292S519

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Abstract: It is implemented into low Power Verilog Architecture to the area for digital images Process application, In the matrix multiplications are one of the key arithmetically operations. And the constructed into VLSI architecture for Low Power, High Speed & Lowarea, Matrices Multiplications designed into become rare. In the projects, is a simple work of fiction in Verilog architectures with Floating point matrix multiplier be presents. The designs into consider as Pseudo codes with the matrix multiplications, CSD multiplication algorithms with power reductions, Convention floating points as number formatting & Pipeline concept with as improves speeds. In the Floating point matrix multiplier design as appropriate with anyone orbitrary sizes of the matrix among the followed matrices rule. It is designed may also gives as higher precision outputs. The simulation result is perfect matched into the MATLAB result.

Keywords: Floating Point Matrix Multiplier (FPMM), Canonic Signed Digit (CSD).
Scope of the Article: Image Security