Energy-Efficient and High-throughput Implementations of Lightweight Block Cipher
Pulkit Singh1, Piyush Modi2, Bibhudendra Acharya3, Rahul Kumar Chaurasiya4
1Pulkit Singh, Department of Electronics & Communication Engineering, National Institute of Technology, Raipur (Chhattisgarh), India.
2Piyush Modi, Department of Electronics & Communication Engineering, National Institute of Technology, Raipur (Chhattisgarh), India.
3Bibhudendra Acharya, Department of Electronics & Communication Engineering, National Institute of Technology, Raipur (Chhattisgarh), India.
4Rahul Kumar Chaurasiya, Department of Electronics & Communication Engineering, Malaviya National Institute of Technology, Raipur (Chhattisgarh), India.
Manuscript received on 03 December 2019 | Revised Manuscript received on 11 December 2019 | Manuscript Published on 31 December 2019 | PP: 35-41 | Volume-9 Issue-2S December 2019 | Retrieval Number: B10221292S19/2019©BEIESP | DOI: 10.35940/ijitee.B1022.1292S19
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open-access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Security in resource-constrained devices has drawn the great attentions to researchers in recent years. To make secure transmission of critical information in such devices, lightweight cryptography algorithms come in light to large extend. KLEIN has been popular lightweight block cipher used to overcome such issues. In this paper, different architectures of KLEIN block cipher are presented. One of designs enhances the efficiency with regard to the throughput at the expense of a larger area. In order to make such designs, the pipelined registers are placed on different positions in datapath algorithm. The proposed design transforms the data input to protected output with the speed of 2414.13 Mbps for xc5vlx50t-3ff1136 device. In addition, the second design implementation completes either one or more than one round in only one clock and gives energy-efficient and high throughput implementations. Due to this, a trade-off between area and speed can be analyzed for high-speed applications. Moreover, this proposed design shows that with increasing the area of cipher implementation results in more transformation of plaintext into ciphertext. All results are verified and simulated for various families of Xilinx ISE design suite.
Keywords: FPGA, KLEIN Cipher, Lightweight Algorithm, Throughput, Resource-constrained Environments, Security, Symmetric Encryption.
Scope of the Article: Economics of Energy Harvesting Communications