Low Voltage High Performance Comparator
K V K V L. Pavan Kumar1, V S V Prabhakar2, B Naga Vardhan3, Ch Murali Krishna4, N S S Nandini5
1K V K V L Pavan Kumar*, Asst. Professor, Department of Electronics and Communication Engineering, Koneru Lakshmaiah Education and Foundation, Guntur, India.
2V S V Prabhakar Professor, Department of Electronics and Communication Engineering, Koneru Lakshmaiah Education and Foundation, Guntur, India.
3B Naga Vardhan, Students, Department of Electronics and Communication Engineering, Koneru Lakshmaiah Education and Foundation, Guntur, India.
4Ch Murali Krishna, Students, Department of Electronics and Communication Engineering, Koneru Lakshmaiah Education and Foundation, Guntur, India.
5N S S Nandini, Students, Department of Electronics and Communication Engineering, Koneru Lakshmaiah Education and Foundation, Guntur, India.
Manuscript received on November 13, 2019. | Revised Manuscript received on 22 November, 2019. | Manuscript published on December 10, 2019. | PP: 1515-1519 | Volume-9 Issue-2, December 2019. | Retrieval Number: B7224129219/2019©BEIESP | DOI: 10.35940/ijitee.B7224.129219
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: A comparator has been proposed using the dynamic bias concept. The proposed comparator operates on low power with minimum delay. It describes the comparison of power and delay characteristics between the dynamic bias model, elzakker circuit and two stage dynamic comparator circuits. This is achieved by enhancing the total effective transconductance with in the circuit. All these circuits were simulated at 130nm technology with a supply voltage of 1.2V.
Keywords: Dynamic Bias, Double-tail Latch-type Comparator, Elzakker Comparator, Analog-to-Digital Converter (ADC).
Scope of the Article: Foundations Dynamics