An Enhanced Low Power Dual Data Injection Technique for Coarse – Grained Reconfigurable Architecture
S.Munaf1, A.Bharathi2, A.N.Jayanthi3
1Mr.S.Munaf*, Assistant Professor(Sr.Gr),Department of ECE, Sri Ramakrishna Institute of Technology, Coimbatore, India.
2Dr.A.Bharathi, Professor, Department of Information Technology, Bannari Amman Institute of Technology, Sathyamangalam, India.
3Dr.A.N.Jayanthi, Associate Professor, Department of ECE, Sri Ramakrishna Institute of Technology, Coimbatore, India.
Manuscript received on November 12, 2019. | Revised Manuscript received on 24 November, 2019. | Manuscript published on December 10, 2019. | PP: 4421-4424 | Volume-9 Issue-2, December 2019. | Retrieval Number: B7299129219/2019©BEIESP | DOI: 10.35940/ijitee.B7299.129219
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Oarse-gr ained reconfigurable architectures (CGRA) having a well-organized, more efficient configurable array of processing unit and high speed cache unit. The processing unit performs required arithmetic and logic operations. Now a day’s video processing applications power consumption plays an important role. We propose Double Data Rate Synchronous Memory architecture can address and reduce the power consumption caused by reconfiguration. An input data bits are injecting on the data bus in the interval of low to high and high low clock period. All modules have been designed and implemented in vertex using behavioral level with VHDL coding and to Simulate in Xilinx ISE navigator.
Keywords: Low Power VLSI Architecture ,CGRA, DDR SRAM Controller.
Scope of the Article: Network Architectures