Design and Development of a Very Large Scale Integrated Circuit Architecture for a Digital Image Compression and Realization on Field Programmable Gate Array
Premachand D R1, U. Eranna2

1Premachand D R*, Associate Professor, Department of ECE, BITM, Ballari, India.
2U. Eranna, Professor and Head, Department of ECE, BITM, Bellari, India.
Manuscript received on December 13, 2019. | Revised Manuscript received on December 21, 2019. | Manuscript published on January 10, 2020. | PP: 3516-3522 | Volume-9 Issue-3, January 2020. | Retrieval Number: B7608129219/2020©BEIESP | DOI: 10.35940/ijrte.B7608.018520
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Abstract: The domain of image signal processing, image compression is the significant technique, which is mainly invented to reduce the redundancy of image data in order to able to transmit the image pixels with high quality resolution. The standard image compression techniques like losseless and lossy compression technique generates high compression ratio image with efficient storage and transmission requirement respectively. There are many image compression technique are available for example JPEG, DWT and DCT based compression algorithms which provides effective results in terms of high compression ratio with clear quality image transformation. But they have more computational complexities in terms of processing, encoding, energy consumption and hardware design. Thus, bringing out these challenges, the proposed paper considers the most prominent research papers and discuses FPGA architecture design and future scope in the state of art of image compression technique. The primary aim to investigate the research challenges toward VLSI designing and image compression. The core section of the proposed study includes three folds viz standard architecture designs, related work and open research challenges in the domain of image compression.
Keywords: Image Compression, JPEG, Wavelet Transform, Energy Efficiency, Storage, VLSI Architecture
Scope of the Article: Nanometer-Scale Integrated Circuits