FPGA IMPLEMENTATION OF LOW POWER PIPELINED 32-BIT RISC PROCESSOR
Preetam Bhosle1, Hari Krishna Moorthy2
1Preetam Bhosle, Department of Electronics and Communication Engineering, , School of Engineering and Technology, Jain University Bangalore, India.
2Asst. Prof. Hari Krishna Moorthy, Department of Electronics and Communication Engineering, School of Engineering and Technology, Jain University, Bangalore, India.
Manuscript received on August 04, 2012. | Revised Manuscript received on August 09, 2012. | Manuscript published on August 10, 2012. | PP: 1-4 | Volume-1 Issue-3, August 2012. | Retrieval Number: C0208071312/2012©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: This paper presents the design and implementation of a low power pipelined 32-bit High performance RISC Core. The various blocks include the Fetch, Decode, Execute and Memory Read / Write Back to implement 4 stage pipelining. In this paper we are proposing low power design technique in front end process. Harvard architecture is used which has distinct program memory space and data memory space. Low power consumption helps to reduce the heat dissipation, lengthen battery life and increase device reliability. To minimize the power of RISC Core, clock gating technique is used in the architectural level which is an efficient low power technique. 7-SEG LEDs are connected to the RISC IO interface for testing purpose, Verilog code is simulated using Modelsim and then implementation is done using Altera Quartus II and Altera FPGA board.
Keywords: Architectural level power reduction, Auto branch prediction, Clock Gating, High performance architecture.