ASIC Implementation of HDB3 Codec
Meshram Vaibhav Bhimrao1, Ramesh T2
1Mr. Meshram Vaibhav Bhimrao, VLSI design and Embedded systems/ visvesvaraya technological university/ UTL Technological Ltd.,Bangalore, India.
2Mr. Ramesh T., VLSI design and Embedded systems/ visvesvaraya technological university/ UTL Technological Ltd., Bangalore, India
Manuscript received on August 01, 2012. | Revised Manuscript received on August 08, 2012. | Manuscript published on August 10, 2012. | PP: 30-35 | Volume-1 Issue-3, August 2012. | Retrieval Number: C0209071312/2012©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: This paper demonstrates the working of HDB3 encoder & decoder and also its implementation at chip level. The HDB3 code consist of 3 modules namely violation module, balance module and polarity correction module. The decoder consists of violation detection module, balance detection module and polarity detection module. The encoder design accepts serial data from the information source in binary format. HDB3 encoder encodes the binary data into two bit symbol data. The encoder data is transmitted over a physical channel. At receiver’s end when the data is present, the decoder detects the violation symbol and balance symbol using the violation and balance detection module. The polarity is restored by the polarity detection module. The HDB3 codec is a modified AMI generator, the design is targeted on 180nm technology provided by JAZZ foundry. The HDB3 codec’s front-end design development and verification is carried out using Questa Sim simulator. ASIC implementation of HDB3 codec is done using SYNOPSYS tools.
Keywords: HDB3 codec.